63: unit = DEV_ADC_3;
64: } else if( in_w(ADC_ISR(DEV_ADC_1))) {
65: unit = DEV_ADC_1;
66: } else if( in_w(ADC_ISR(DEV_ADC_2))) {
67: unit = DEV_ADC_2;
75:
76: out_w(ADC_ISR(unit), 0x000007FF); // Clear all interrupt flag.
77: ClearInt((unit == DEV_ADC_3)?INTNO_INTADC3:INTNO_INTADC1_2);
133: /* Initialize interrupt */
134: out_w(ADC_ISR(unit), 0x000007FF); // Clear all interrupt flag.
135: out_w(ADC_IER(unit), ADC_IER_ADRDYIE | ADC_IER_EOCIE); // Set Interrupt mask.
161: out_w(ADC_CR(unit), ADC_CR_ADDIS); // Set ADDIS
162: while(in_w(ADC_ISR(unit)) & ADC_ISR_ADRDY); // Wait until ADEN is clear
163: }