241: wait_mac(inf);
242: OutW(MAC_CSR_DATA, dat);
243: OutW(MAC_CSR_CMD, reg | MAC_CSR_CMD_BUSY);
244: wait_mac(inf);
256: wait_mac(inf);
257: OutW(MAC_CSR_CMD, reg | MAC_CSR_CMD_BUSY | MAC_CSR_CMD_READ);
258: wait_mac(inf);
321: wait_srom(inf);
322: OutW(E2P_CMD, (E2P_CMD_BUSY | E2P_CMD_READ |
323: E2P_CMD_TMO | E2P_CMD_ADDR(adr)));
337: if (InW(PMT_CTRL) & PMT_CTRL_PM_MODE(3)) {
338: OutW(BYTE_TEST, BYTE_TEST_MAGIC); /* wake-up! */
339: wait_reg(inf, PMT_CTRL, PMT_CTRL_READY, PMT_CTRL_READY);
342: /* Initialize PHY */
343: OutW(PMT_CTRL, PMT_CTRL_PHY_RST);
344: WaitUsec(100);
384: /* Disable interrupt handler */
385: OutW(INT_EN, 0);
386: inf->IntMask = 0;
393: /* Initialize */
394: OutW(HW_CFG, HW_CFG_SRST);
395: wait_reg(inf, HW_CFG, HW_CFG_SRST, 0);
400:
401: OutW(HW_CFG, HW_CFG_SF | HW_CFG_TX_FIF_SZ(TX_FIFO_SIZE) |
402: HW_CFG_PHY_CLK_INT);
403: OutW(AFC_CFG, 0x006e3740);
404: OutW(FIFO_INT, FIFO_INT_TSFL(0) | FIFO_INT_RSFL(0));
405: OutW(RX_CFG, RX_CFG_ALIGN_4 | RX_CFG_DUMP | RX_CFG_DOFF(0));
406: wait_reg(inf, RX_CFG, RX_CFG_DUMP, 0);
407: OutW(TX_CFG, TX_CFG_SDUMP | TX_CFG_DDUMP);
408: wait_reg(inf, TX_CFG, TX_CFG_SDUMP | TX_CFG_DDUMP, 0);
409: #ifdef GPIO_CFG_VAL
410: OutW(GPIO_CFG, GPIO_CFG_VAL);
411: #else
412: OutW(GPIO_CFG, 0x70000000); /* LED1-3 enable */
413: #endif
439: /* Enable both transmitter and receiver */
440: OutW(TX_CFG, TX_CFG_ON);
441: cr = MAC_CR_TXEN | MAC_CR_RXEN;
446: #ifdef IRQ_CFG_VAL
447: OutW(IRQ_CFG, IRQ_CFG_IRQ_EN | IRQ_CFG_VAL);
448: #else
449: OutW(IRQ_CFG, (IRQ_CFG_INT_DEAS(22) |
450: IRQ_CFG_IRQ_EN | IRQ_CFG_IRQ_TYPE)); /* Low/Push-Pull */
453: INT_TSFF | INT_TSFL | INT_RSFF | INT_RSFL);
454: OutW(INT_EN, inf->IntMask);
455: fin0:
555: if (len >= 4) {
556: OutW(RX_DP_CTL, RX_DP_CTL_FFWD);
557: wait_reg(inf, RX_DP_CTL, RX_DP_CTL_FFWD, 0);
615: sts = InW(INT_STS);
616: OutW(INT_STS, sts & ~inf->IntMask);
617:
631: smsc9118_receive(inf);
632: OutW(INT_STS, sts & (INT_RSFF | INT_RSFL));
633: }
638: smsc9118_sendcomplete(inf);
639: OutW(INT_STS, sts & (INT_TSFF | INT_TSFL));
640: }
671: /* Avoid conflict with the interrupt handler */
672: OutW(INT_EN, 0);
673:
680: /* Write TX Command A/B */
681: OutW(TX_DATA, (TX_CMDA_ALIGN_4 | TX_CMDA_OFFSET(ofs) |
682: TX_CMDA_FS | TX_CMDA_LS | TX_CMDA_BUFSZ(len)));
683: OutW(TX_DATA, TX_CMDB_PADDIS | TX_CMDB_PKTSZ(len));
684:
689: }
690: OutW(TX_DATA, d);
691: }
693: /* Middle of data (transfer by 4-byte units) */
694: for (; len > 3; len -= 4, buf += 4) OutW(TX_DATA, *(UW *)buf);
695:
704: }
705: OutW(TX_DATA, d);
706: }
716: /* Enable interrupt */
717: OutW(INT_EN, inf->IntMask);
718: inf->stinf.txpkt++;
789: /* Disable interrupt, stop both transmitter and receiver */
790: OutW(INT_EN, 0); /* disable intr */
791: OutW(TX_CFG, TX_CFG_STOP); /* stop xmit */
792: wait_reg(inf, TX_CFG, TX_CFG_STOP, 0);