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110: 111: #define IT0_IENS0 SINT(0xE200) /* RW ACPU Secure enable interrupt 0 */ 112: #define IT0_IENS1 SINT(0xE204) /* RW ACPU Secure enable interrupt 1 */
60: 61: #define IT0_IENS0 SINT(0xE200) /* RW ACPU Secure enable interrupt 0 */ 62: #define IT0_IENS1 SINT(0xE204) /* RW ACPU Secure enable interrupt 1 */