94: {"R7 ", R_GEN + 0x07 + R_LF }, // 7
95: {"R8 ", R_GEN + SPEC(0x00) }, // 8
96: {"R9 ", R_GEN + SPEC(0x01) }, // 9
97: {"R10/SL ", R_GEN + SPEC(0x02) }, // 10
98: {"R11/FP ", R_GEN + SPEC(0x03) + R_LF }, // 11
99: {"R12/IP ", R_GEN + SPEC(0x04) }, // 12
100: {"R13/SP ", R_GEN + SPEC(0x05) }, // 13
101: {"R14/LR ", R_GEN + SPEC(0x06) }, // 14
102: {"R15/PC ", R_GEN + ixPC + R_LF }, // 15
129: {"CPSR ", R_CTL + ixCPSR + R_GAP }, // 38
130: {"SPSR ", R_CTL + SPEC(0x08) }, // 39
131: {"SPSR_FIQ", R_CTL + ixFIQ - 1 }, // 40
136:
137: {"SCTLR ", R_CTL + SPEC(0x0F) + 0 + R_GAP }, // 45
138: {"TTBR0 ", R_CTL + ixCP15 + 1 + R_ONLY }, // 46
209: // normal register
210: if (i < SPEC(0)) return regStack[i & 0xff];
211:
216: switch(i) {
217: case SPEC(0x00): // R8
218: case SPEC(0x01): // R9
219: case SPEC(0x02): // R10
220: case SPEC(0x03): // R11
221: case SPEC(0x04): // R12
222: if (ix != ixFIQ) ix = ixUSR;
223: case SPEC(0x05): // R13
224: case SPEC(0x06): // R14
225: return regStack[ix + i - SPEC(0)];
226: case SPEC(0x08): // SPSR
227: if (ix == ixUSR) return 0; // undefined
229: return regStack[ix + 4];
230: case SPEC(0x0F): // CP15 R1
231: return regStack[ixCP15R1];
245:
246: if (i < SPEC(0)) { // normal register
247: regStack[i & 0xff] = val;
255: switch(i) {
256: case SPEC(0x00): // R8
257: case SPEC(0x01): // R9
258: case SPEC(0x02): // R10
259: case SPEC(0x03): // R11
260: case SPEC(0x04): // R12
261: if (ix != ixFIQ) ix = ixUSR;
262: case SPEC(0x05): // R13
263: case SPEC(0x06): // R14
264: regStack[ix + i - SPEC(0x00)] = val;
265: break;
266: case SPEC(0x08): // SPSR
267: if (ix == ixUSR) break; // undefined
270: break;
271: case SPEC(0x0F): // CP15 R1
272: regStack[ixCP15R1] &= MASK_CACHEMMU;