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25: #if _TEF_EM1D_ 26: #define SC_DATA _IOADR(0) /* Data register R/W */ 27: #define SC_INTE _IOADR(1) /* Interrupt-enabled register R/W */ 28: #define SC_INTS _IOADR(2) /* Interrupt ident register R */ 29: #define SC_FCTL _IOADR(3) /* FIFO control register W */ 30: #define SC_LCTL _IOADR(4) /* Line control register R/W */ 31: #define SC_MCTL _IOADR(5) /* Modem control register R/W */ 32: #define SC_LSTS _IOADR(6) /* Line status register R */ 33: #define SC_MSTS _IOADR(7) /* Modem status register R */ 34: #define SC_SCRA _IOADR(8) /* Temporary data register R/W */ 35: #define SC_DIVL _IOADR(9) /* Freq dividing count lower R/W */ 36: #define SC_DIVH _IOADR(10) /* Freq dividing count upper R/W */ 37: #else 38: #define SC_DATA _IOADR(0) /* Data register R/W */ 39: #define SC_INTE _IOADR(1) /* Interrupt-enabled register R/W */ 40: #define SC_INTS _IOADR(2) /* Interrupt ident register R */ 41: #define SC_FCTL _IOADR(2) /* FIFO control register W */ 42: #define SC_LCTL _IOADR(3) /* Line control register R/W */ 43: #define SC_MCTL _IOADR(4) /* Modem control register R/W */ 44: #define SC_LSTS _IOADR(5) /* Line status register R */ 45: #define SC_MSTS _IOADR(6) /* Modem status register R */ 46: #define SC_SCRA _IOADR(7) /* Temporary data register R/W */ 47: #define SC_DIVL _IOADR(0) /* Freq dividing count lower R/W */ 48: #define SC_DIVH _IOADR(1) /* Freq dividing count upper R/W */ 49: #endif