69: out_b(SCIFA_FTDR, *buf++);
70: and_h(SCIFA_FSR, ~(FSR_TEND|FSR_TDFE));
71: }
80: /* Clear error */
81: and_h(SCIFA_SCR, ~SCR_RE); /* Stop receive */
82: or_h(SCIFA_FCR, FCR_RFRST); /* Reset FIFO */
83: and_h(SCIFA_FCR, ~FCR_RFRST);
84: and_h(SCIFA_FSR, ~FSR_ERROR); /* Clear error bit */
85: and_h(SCIFA_LSR, ~LSR_ORER); /* Clear overrun error */
86: or_h(SCIFA_SCR, SCR_RE); /* Start receive */
89: *buf++ = in_b(SCIFA_FRDR); /* Read received data */
90: and_h(SCIFA_FSR, ~(FSR_RDF|FSR_DR)); /* Clear RDF/DR */
91: }
99:
100: and_h(SCIFA_FSR, ~(FSR_ER | FSR_BRK | FSR_DR)); /* Clear error bit */
101: and_h(SCIFA_LSR, ~LSR_ORER); /* Clear overrun error */
102: