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81: and_h(SCIFA_SCR, ~SCR_RE); /* Stop receive */ 82: or_h(SCIFA_FCR, FCR_RFRST); /* Reset FIFO */ 83: and_h(SCIFA_FCR, ~FCR_RFRST); 85: and_h(SCIFA_LSR, ~LSR_ORER); /* Clear overrun error */ 86: or_h(SCIFA_SCR, SCR_RE); /* Start receive */ 87: } 109: out_h(SCIFA_FCR, 0x00000030); /* Release FIFO reset */ 110: or_h(SCIFA_SPTR, 0x00000003); /* Break output settings */ 111: out_h(SCIFA_SCR, (SCR_TE|SCR_RE)); /* Enable send/receive */