231: */
232: #define wait_mac(inf) wait_reg((inf), MAC_CSR_CMD, MAC_CSR_CMD_BUSY, 0)
233:
311: */
312: #define wait_srom(inf) wait_reg((inf), E2P_CMD, E2P_CMD_BUSY, 0)
313:
338: OutW(BYTE_TEST, BYTE_TEST_MAGIC); /* wake-up! */
339: wait_reg(inf, PMT_CTRL, PMT_CTRL_READY, PMT_CTRL_READY);
340: }
344: WaitUsec(100);
345: wait_reg(inf, PMT_CTRL, PMT_CTRL_PHY_RST, 0);
346:
394: OutW(HW_CFG, HW_CFG_SRST);
395: wait_reg(inf, HW_CFG, HW_CFG_SRST, 0);
396: wait_reg(inf, PMT_CTRL, PMT_CTRL_READY, PMT_CTRL_READY);
397: if (InW(HW_CFG) & HW_CFG_SRST_TO) inf->BadState = 1;
405: OutW(RX_CFG, RX_CFG_ALIGN_4 | RX_CFG_DUMP | RX_CFG_DOFF(0));
406: wait_reg(inf, RX_CFG, RX_CFG_DUMP, 0);
407: OutW(TX_CFG, TX_CFG_SDUMP | TX_CFG_DDUMP);
408: wait_reg(inf, TX_CFG, TX_CFG_SDUMP | TX_CFG_DDUMP, 0);
409: #ifdef GPIO_CFG_VAL
556: OutW(RX_DP_CTL, RX_DP_CTL_FFWD);
557: wait_reg(inf, RX_DP_CTL, RX_DP_CTL_FFWD, 0);
558: } else {
791: OutW(TX_CFG, TX_CFG_STOP); /* stop xmit */
792: wait_reg(inf, TX_CFG, TX_CFG_STOP, 0);
793: poke_mac(inf, MAC_CR,