75:
76: out_w(ADC_ISR(unit), 0x000007FF); // Clear all interrupt flag.
77: ClearInt((unit == DEV_ADC_3)?INTNO_INTADC3:INTNO_INTADC1_2);
91:
92: out_w(ADC_SQR1(unit), size-1); // Set channel sequence length.
93:
106: tk_can_wup(TSK_SELF);
107: out_w(ADC_CR(unit), ADC_CR_ADSTART | ADC_CR_ADVREGEN); // Start Covert
108: for( rtn = 0; rtn < size; rtn++) {
129: /* Set sampling time */
130: out_w(ADC_SMPR1(unit), ll_devcb[unit].smpr1);
131: out_w(ADC_SMPR2(unit), ll_devcb[unit].smpr2);
132:
133: /* Initialize interrupt */
134: out_w(ADC_ISR(unit), 0x000007FF); // Clear all interrupt flag.
135: out_w(ADC_IER(unit), ADC_IER_ADRDYIE | ADC_IER_EOCIE); // Set Interrupt mask.
136: if(unit != DEV_ADC_3) {
143: ll_devcb[unit].wait_tskid = tk_get_tid();
144: out_w(ADC_CR(unit), ADC_CR_ADEN | ADC_CR_ADVREGEN); // Set ADEN
145:
160: /* Disable ADC */
161: out_w(ADC_CR(unit), ADC_CR_ADDIS); // Set ADDIS
162: while(in_w(ADC_ISR(unit)) & ADC_ISR_ADRDY); // Wait until ADEN is clear
224: ccipr = in_w(RCC_CCIPR) & ~RCC_CCIPR_ADCSEL;
225: out_w(RCC_CCIPR, ccipr | (DEVCNF_ADCSEL << 28));
226:
233: /* ADC Power-On */
234: out_w(ADC_CR(unit), 0); // DEEPPWD = 0
235: out_w(ADC_CR(unit), ADC_CR_ADVREGEN); // ADVREGEN = 1
236:
238: if(uninit) {
239: out_w(ADC_CCR,
240: ((DEVCNF_ADC_CKMODE & 0x03)<< 16) // ADC clock mode
245: /* ADC calibration */
246: out_w(ADC_CR(unit), ADC_CR_ADVREGEN | ADC_CR_ADCAL); // ADCAL = 1
247: while( in_w(ADC_CR(unit)) & ADC_CR_ADCAL); // Wait until ADCAL is clear