60: out_b(RIIC_ICDRT, (ll_devcb.sadr|1));
61: reg = in_b(RIIC_ICIER);
62: out_b(RIIC_ICIER, (reg | RIIC_ICIER_RIE) & ~RIIC_ICIER_TIE);
73: }
74: reg = in_b(RIIC_ICIER);
75: out_b(RIIC_ICIER, (reg | RIIC_ICIER_TEIE) & ~RIIC_ICIER_TIE);
90: case I2C_STS_STOP:
91: reg = in_b(RIIC_ICIER);
92: out_b(RIIC_ICIER, (reg & ~RIIC_ICIER_TEIE) |RIIC_ICIER_SPIE);
119: }
120: in_b(RIIC_ICDRR); // Dummy read
121: break;
130: }
131: *ll_devcb.rbuf++ = in_b(RIIC_ICDRR);
132: ll_devcb.rdat_num--;
136: *(UB*)RIIC_ICSR2 &= ~RIIC_ICSR2_STOP;
137: reg = in_b(RIIC_ICIER);
138: out_b(RIIC_ICIER, (reg | RIIC_ICIER_SPIE) & ~RIIC_ICIER_RIE);
139: *(UB*)RIIC_ICCR2 |= RIIC_IICR2_SP;
140: *ll_devcb.rbuf++ = in_b(RIIC_ICDRR);
141: *(UB*)RIIC_ICMR3 &= ~RIIC_ICMR3_WAIT;
150:
151: reg = in_b(RIIC_ICSR2);
152:
179:
180: if( in_b(RIIC_ICCR2) & RIIC_IICR2_BBSY) {
181: ll_devcb.ioerr = E_BUSY; /* I2C bus busy */
197: out_b( RIIC_ICIER, 0);
198: reg = in_b(RIIC_ICSR2);
199: out_b( RIIC_ICSR2, reg & ~RIIC_ICSR2_STOP & ~RIIC_ICSR2_NACKF);