56: if(ll_devcb.sdat_num > 0 ) { /* Send */
57: out_b(RIIC_ICDRT, ll_devcb.sadr);
58: ll_devcb.state = I2C_STS_SEND;
59: } else { /* Receive */
60: out_b(RIIC_ICDRT, (ll_devcb.sadr|1));
61: reg = in_b(RIIC_ICIER);
62: out_b(RIIC_ICIER, (reg | RIIC_ICIER_RIE) & ~RIIC_ICIER_TIE);
63: ll_devcb.state = I2C_STS_RECV | I2C_STS_TOP;
74: reg = in_b(RIIC_ICIER);
75: out_b(RIIC_ICIER, (reg | RIIC_ICIER_TEIE) & ~RIIC_ICIER_TIE);
76: }
77: out_b(RIIC_ICDRT, *(ll_devcb.sbuf)++);
78: break;
91: reg = in_b(RIIC_ICIER);
92: out_b(RIIC_ICIER, (reg & ~RIIC_ICIER_TEIE) |RIIC_ICIER_SPIE);
93: *(UB*)RIIC_ICCR2 |= RIIC_IICR2_SP; // Stop condition
96: case I2C_STS_RESTART:
97: out_b( RIIC_ICIER , RIIC_ICIER_TIE | RIIC_ICIER_NAKIE); /* Enable TXI & NAKI */
98: *(UB*)RIIC_ICCR2 |= RIIC_IICR2_RS; // Rester condition
137: reg = in_b(RIIC_ICIER);
138: out_b(RIIC_ICIER, (reg | RIIC_ICIER_SPIE) & ~RIIC_ICIER_RIE);
139: *(UB*)RIIC_ICCR2 |= RIIC_IICR2_SP;
156: }
157: out_b( RIIC_ICIER, 0);
158: if(ll_devcb.wait_tskid) {
165: *(UB*)RIIC_ICSR2 &= ~RIIC_ICSR2_STOP;
166: out_b( RIIC_ICIER, RIIC_ICIER_SPIE);
167: *(UB*)RIIC_ICCR2 |= RIIC_IICR2_SP; /* Stop condition */
187:
188: out_b( RIIC_ICIER , RIIC_ICIER_TIE | RIIC_ICIER_NAKIE); /* Enable TXI & NAKI */
189: // out_b( RIIC_ICIER , 0xFF); /* Enable TXI & NAKI */
196:
197: out_b( RIIC_ICIER, 0);
198: reg = in_b(RIIC_ICSR2);
199: out_b( RIIC_ICSR2, reg & ~RIIC_ICSR2_STOP & ~RIIC_ICSR2_NACKF);
200:
227: /* I2C Device reset */
228: out_b( RIIC_ICCR1, RIIC_ICCR1_IICRST | RIIC_ICCR1_SOWP);
229: out_b( RIIC_ICCR1, RIIC_ICCR1_IICRST| RIIC_ICCR1_ICE | RIIC_ICCR1_SOWP);
230:
231: /* I2C Initial setting */
232: out_b( RIIC_ICSER, 0);
233: out_b( RIIC_ICMR1, DEVCNF_I2C_CKS<<4 );
234: //out_b( RIIC_ICMR3, RIIC_ICMR3_ACKWP);
235: out_b( RIIC_ICBRH, RIIC_ICBRH_INI);
236: out_b( RIIC_ICBRL, RIIC_ICBRL_INI);
237:
238: /* Interrupt initialize */
239: out_b( RIIC_ICIER, 0);
240: out_b( RIIC_ICSR2, 0);
241: EnableInt( INTNO_RIIC_EEI, DEVCNF_I2C_INTPRI);
246: /* Release reset */
247: out_b( RIIC_ICCR1, RIIC_ICCR1_ICE | RIIC_ICCR1_SOWP);
248: break;
305: /* Set pin-function P16 = SCL0, P17 = SDA0 */
306: out_b(MPC_PWPR, 0); // PWPR.B0WI = 0
307: out_b(MPC_PWPR, MPC_PWMR_PFSWE); // PWPR.PFSWE = 1
308: out_b(MPC_P1nPFS(6), 0x0F); // P16 = SCL0
309: out_b(MPC_P1nPFS(7), 0x0F); // P17 = SDA0
310: out_b(MPC_PWPR, MPC_PWMR_B0WI); // PWPR.PFSWE = 0, PWPR.B0WI = 1
311:
312: out_b(PORT1_ODR1, 0x50); // Set to open drain
313: out_b(PORT1_PMR, 0xC0); // Set as peripheral function
314: