108: } else if( i2c_st & I2C_ISR_TXIS) { /* TX interrupt */
109: out_w(I2C_TXDR(unit),*p_cb->sbuf++);
110: if(--(p_cb->sdat_num) <= 0) { /* final data ? */
111: if(p_cb->rdat_num == 0) {
112: out_w(I2C_CR1(unit), I2C_CR1_PE);
113: p_cb->state = I2C_STS_STOP;
115: } else {
116: out_w(I2C_CR1(unit), I2C_CR1_PE | I2C_CR1_TCIE | I2C_CR1_RXIE | I2C_CR1_NACKIE | I2C_CR1_ERRIE );
117: }
120: } else if( i2c_st & I2C_ISR_TC) { /* Transfer complete */
121: out_w(I2C_CR1(unit), I2C_CR1_PE | I2C_CR1_RXIE | I2C_CR1_NACKIE | I2C_CR1_ERRIE );
122: p_cb->state = I2C_STS_START;
127: if(--(p_cb->rdat_num) <= 0) { /* final data ? */
128: out_w(I2C_CR1(unit), I2C_CR1_PE);
129: p_cb->state = I2C_STS_STOP;
132: } else { /* Error */
133: out_w(I2C_CR1(unit), I2C_CR1_PE);
134: p_cb->ioerr = E_IO;
136:
137: out_w(I2C_ICR(unit), I2C_ICR_ALL); // Clear all Interrupt flag
138: ClearInt(intno); // Clear interrupt
164:
165: out_w(I2C_ICR(unit), I2C_ICR_ALL); // Clear all Interrupt flag
166: ClearInt(intno); // Clear interrupt
167:
168: out_w(I2C_CR1(unit), I2C_CR1_PE);
169:
189: /* I2C Device enable */
190: out_w(I2C_CR1(unit), I2C_CR1_PE | I2C_CR1_TXIE | I2C_CR1_RXIE | I2C_CR1_NACKIE | I2C_CR1_ERRIE );
191:
202: }
203: out_w(I2C_CR2(unit), i2c_ctl);
204: p_cb->state = I2C_STS_SEND;
207: p_cb->state = I2C_STS_RECV;
208: out_w(I2C_CR2(unit), i2c_ctl);
209: }
210:
211: out_w(I2C_CR2(unit), i2c_ctl | I2C_CR2_START);
212: EI(imask);
227:
228: out_w(I2C_CR1(unit), 0); /* I2C Device disable */
229:
257: /* I2C Initial setting */
258: out_w(I2C_TIMINGR(unit), I2C_TIMINGR_INIT);
259:
309: ccipr = in_w(RCC_CCIPR) & ~(RCC_CCIPR_I2CSEL << (unit<<1));
310: out_w(RCC_CCIPR, ccipr |(DEVCNF_I2CSEL << (12 + (unit<<1))));
311: