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29: /* set Timer Count */ 30: out_h(CMT0_COR, EXTAL_CLOCK/PCLK_DIV/1000*TIMER_PERIOD/CMCR_DIV - 1); 31: 32: /* Interrupt is Enable, Set Frequency Dividing */ 33: out_h(CMT0_CR, CMT0_CR_CMIE | CMCR_CKS_PLCK8); 34: 38: /* Start timer count */ 39: out_h(CMT_STR0, CMT_STR0_STR0); 40: } 73: 74: out_h(CMT0_CR, 0); /* Disable compare match interrupt */ 75: cmstr0 = in_h(CMT_STR0) & ~(CMT_STR0_STR0); 76: out_h(CMT_STR0, cmstr0); /* Stop timer count */ 77: }