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68: } while(!(d&FSR_TDFE)); 69: out_b(SCIFA_FTDR, *buf++); 70: and_h(SCIFA_FSR, ~(FSR_TEND|FSR_TDFE)); 105: out_h(SCIFA_SMR, 0); /* UART mode, DATA=8bit, Parity=NONE, STOP=1, CLOCK=P1φ/1 (66.67MHz) */ 106: out_b(SCIFA_SEMR, 0); /* Baud rate generator = normal mode, Operates with a frequency 16 times the transfer rate as the basic clock */ 107: out_b(SCIFA_BRR, 17); /* Dividend ratio */ 108: