96: {
97: out_h(SCIFA_SCR, 0); /* Stop send/receive, Select internal clock */
98: out_h(SCIFA_FCR, FCR_RFRST|FCR_TFRST); /* Reset FIFO */
99:
104: /* P1 clock=66.67MHz CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps */
105: out_h(SCIFA_SMR, 0); /* UART mode, DATA=8bit, Parity=NONE, STOP=1, CLOCK=P1φ/1 (66.67MHz) */
106: out_b(SCIFA_SEMR, 0); /* Baud rate generator = normal mode, Operates with a frequency 16 times the transfer rate as the basic clock */
108:
109: out_h(SCIFA_FCR, 0x00000030); /* Release FIFO reset */
110: or_h(SCIFA_SPTR, 0x00000003); /* Break output settings */
111: out_h(SCIFA_SCR, (SCR_TE|SCR_RE)); /* Enable send/receive */
112: