114: /* generate start condition */
115: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) & ~IICC_ACKE);
116: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) | IICC_STT);
117:
151: /* generate stop condition */
152: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) | IICC_SPT);
153:
197: if (cmd & IIC_TOPDATA) {
198: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) & ~IICC_WTIM);
199: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) | IICC_ACKE);
200: }
202: /* initiate data receive */
203: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) | IICC_WREL);
204: er = wait_int();
215: if ((cmd & IIC_LASTDATA) || er < E_OK) {
216: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) | IICC_WTIM);
217: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) & ~IICC_ACKE);
218: out_w(IIC_IICC(ch), in_w(IIC_IICC(ch)) | IICC_WREL);
219: wait_int();
239: /* initialization */
240: out_w(IIC_IICC(ch), 0); // halt entire operation
241: out_w(IIC_IICCL(ch), IICCL_SMC | IICCL_DFC); // high-speed mode + filter
242: out_w(IIC_IICF(ch), IICF_STCEN | IICF_IICRSV); // force transmission
243: out_w(IIC_IICC(ch), IICC_IICE | IICC_WTIM); // IIC operation, 9 bits mode
244: tk_can_wup(TSK_SELF);
278: fin1:
279: out_w(IIC_IICC(ch), 0); // halt entire operation
280: Unlock(&IICLock[ch]);