54: {
55: OutB(port, InB(port) & ~m);
56: }
58: {
59: OutB(port, InB(port) | m);
60: }
62: {
63: OutB(port, (InB(port) & ~m) | v);
64: }
77:
78: #define ENB_RXINT(li) OutB(SC_INTE, (li->enbint == 0) ? \
79: 0x00 : (IM_LSTS|IM_RCV|IM_MSTS))
80: #define ENB_TXRXINT(li) OutB(SC_INTE, (li->enbint == 0) ? \
81: 0x00 : (IM_LSTS|IM_SND|IM_RCV|IM_MSTS))
82: #define DIS_TXRXINT(li) OutB(SC_INTE, 0x00)
83:
164: /* Clear the pending interrupt */
165: OutB(SC_LCTL, 0x00);
166: InB(SC_LSTS); /* Clear the "IS_LSTS" */
176: /* Check the presence and absence of FIFO */
177: OutB(SC_FCTL, fctl);
178: if ( (InB(SC_INTS) & IS_FIFO) == 0 ) {
190: /* Initialize the serial controller */
191: OutB(SC_LCTL, LC_DLAB);
192: OutB(SC_DIVH, divcnt >> 8); /* Communication speed */
193: OutB(SC_DIVL, divcnt & 0xff);
194: OutB(SC_LCTL, lctl); /* Line mode */
195: OutB(SC_FCTL, (fctl == 0) ? 0 : (fctl|FC_TXCLR|FC_RXCLR));
196: /* Set/Disable the FIFO mode */
198:
199: OutB(SC_MCTL, mctl); /* Modem mode */
200:
257: the all receive FIFO shall be cleared. */
258: OutB(SC_FCTL, fctl|FC_RXCLR);
259: }
342: /* Send the "XON / XOFF" */
343: OutB(SC_DATA, li->flowsts.reqchar);
344: li->flowsts.reqchar = 0;
352: while ( --n >= 0 ) {
353: OutB(SC_DATA, li->ou_buf[
354: OU_PTRMASK(li, li->ou_rptr++)]);
491: ENB_TXRXINT(li); /* Enable the snd/rcv interrupts */
492: OutB(SC_DATA, c);
493: while ( --n > 0 )
494: OutB(SC_DATA, li->ou_buf[OU_PTRMASK(li, li->ou_rptr++)]);
495: return TRUE;
878: DIS_TXRXINT(li);
879: OutB(SC_MCTL, 0x00);
880: }