37: gb = giob[i];
38: out_w(GIO_IDS(gb), 0xffffffff); /* disable interrupt */
39: out_w(GIO_IIA(gb), 0x00000000); /* disassert interrupt pin */
40: out_w(GIO_GSW(gb), 0x00000000); /* disassert FIQ pin */
41: }
43: /* initialize interrupt controller (AINT) */
44: out_w(IT0_IDSS0, 0xffffffff); /* disassert interrupt pin */
45: out_w(IT0_IDSS1, 0xffffffff);
46: out_w(IT0_IDSS2, 0xffffffff);
47: out_w(IT0_IDS0, 0xffffffff); /* disable interrupt */
48: out_w(IT0_IDS1, 0xffffffff);
49: out_w(IT0_IDS2, 0xffffffff);
50: out_w(IT_PINV_CLR0, 0xffffffff); /* reset inverted logic */
51: out_w(IT_PINV_CLR1, 0xffffffff);
52: out_w(IT_PINV_CLR2, 0xffffffff);
53: out_w(IT_LIIR, 0xffffffff); /* clear interrupt */
54: out_w(IT0_IIR, 0xffffffff);
55: out_w(IT0_FIE, 0x00000001); /* enable FIQ */
56:
57: /* enable GPIO interrupt on AINT */
58: out_w(IT0_IENS0, IRQM(26)|IRQM(27)); /* assert interrupt pin */
59: out_w(IT0_IENS1, IRQM(50)|IRQM(51)|IRQM(52)|IRQM(53));
60: out_w(IT0_IENS2, IRQM(79)|IRQM(80));
61: out_w(IT0_IEN0, IRQM(26)|IRQM(27)); /* enable interrupt */
62: out_w(IT0_IEN1, IRQM(50)|IRQM(51)|IRQM(52)|IRQM(53));
63: out_w(IT0_IEN2, IRQM(79)|IRQM(80));
64: