133: {
134: out_w(IT0_IIR, IRQbit(IIC2_IRQ)); // IRQ39 clear
135: return;
140: {
141: out_w(IT_PINV_CLR1, IRQbit(IIC2_IRQ));
142: out_w(IT0_IENS1, IRQbit(IIC2_IRQ));
143: clear_int();
164: /* generate start condition */
165: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
166: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_STT);
167:
172: /* slave address / communication mode transmission */
173: out_w(IIC_IIC(IIC2), addr);
174: er = wait_int();
194: /* generate stop condition */
195: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_SPT);
196:
209: /* data transmission */
210: out_w(IIC_IIC(IIC2), data);
211: er = wait_int();
232: if (attr & IIC_TOPDATA) {
233: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_WTIM);
234: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_ACKE);
235: }
237: /* instruct the reception of data */
238: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
239: er = wait_int();
246: if ((attr & IIC_LASTDATA) || er < E_OK) {
247: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WTIM);
248: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
249: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
250: wait_int();
261: /* initialization default */
262: out_w(IIC_IICC(IIC2), 0); // stop completely
263: out_w(IIC_IICCL(IIC2), IICCL_SMC | IICCL_DFC); // fast mode + filter
264: out_w(IIC_IICF(IIC2), IICF_STCEN | IICF_IICRSV);// forcibly start transmission
265: out_w(IIC_IICC(IIC2), IICC_IICE | IICC_WTIM); // IIC mode, 9bit mode
266: clear_int();
276: {
277: out_w(IIC_IICC(IIC2), 0); // stop completely
278: return;
378: /* enable abort switch interrupt */
379: out_w(GIO_IDT1(GIO_L), 0x00000008); // asynchronous leading-edge high interrupt
380: out_w(GIO_IIR(GIO_L), 0x00000100);
381: out_w(GIO_IIA(GIO_L), 0x00000100);
382: out_w(GIO_IEN(GIO_L), 0x00000100);
383:
411: /* clear interrupt */
412: out_w(GIO_IIR(GIO_L), 0x00000100);
413: