151:
152: er = wait_state(IT0_RAW1, IRQbit(IIC2_IRQ), IRQbit(IIC2_IRQ));
153: clear_int();
168: /* wait for reserving a master */
169: er = wait_state(IIC_IICSE(IIC2), IICSE_MSTS, IICSE_MSTS);
170: if (er < E_OK) goto fin0;
197: /* wait for sending STOP bit(s) */
198: er = wait_state(IIC_IICSE(IIC2), IICSE_SPD, IICSE_SPD);
199:
268: /* wait for bus to become available (since there is only one master, the bus is supposed to be unoccupied) */
269: er = wait_state(IIC_IICF(IIC2), IICF_IICBSY, 0);
270: