gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: 
   15: /*
   16:  *      dev_adc_rza2m.h
   17:  *      A/D converter device driver
   18:  *      System-dependent definition for RZ/A2M
   19:  */
   20: 
   21: #ifndef __DEV_ADC_RZA2M_H__
   22: #define __DEV_ADC_RZA2M_H__
   23: 
   24: #define DEV_ADC_UNITNM  (1)              /* Number of devive units */
   25: #define DEV_ADC_UNIT0   (0)
   26: 
   27: #define ADC_CH_NUM      (8)          /* Number of A/DC chanels */
   28: 
   29: /*
   30:  * ADC registers
   31:  */
   32: #define ADCSR           (0xE8005800)     // A/D control register
   33: #define ADCSR_ADIE      (1<<12)              // Scan end interrupt enabled bit
   34: #define ADCSR_ADST      (1<<15)              // A/DC start bit
   35: #define ADCSR_INI       (0)           // ADCSR init value (ADC stop, Single scan mode)
   36: 
   37: #define ADANSA0         (0xE8005804)
   38: #define ADADS0          (0xE8005808)
   39: #define ADADC           (0xE800580C)
   40: #define ADCER           (0xE800580E)
   41: #define ADSTRGR         (0xE8005810)
   42: #define ADANSB0         (0xE8005814)
   43: #define ADDBLDR         (0xE8005818)
   44: #define ADRD            (0xE800581E)
   45: 
   46: /* A/D dara register ch.0-7 */
   47: #define ADDR(c)         (0xE8005820 + (c<<1))
   48: 
   49: #define ADDISCR         (0xE800587A)
   50: 
   51: #define ADGSPCR         (0xE8005880)
   52: #define ADDBLDRA        (0xE8005884)
   53: #define ADDBLDRB        (0xE8005886)
   54: #define ADWINMON        (0xE800588C)
   55: 
   56: #define ADCMPCR         (0xE8005890)
   57: #define ADCMPANSR0      (0xE8005894)
   58: #define ADCMPLR0        (0xE8005898)
   59: #define ADCMPDR0        (0xE800589C)
   60: #define ADCMPDR1        (0xE800589E)
   61: 
   62: #define ADCMPSR0        (0xE80058A0)
   63: #define ADCMPBNSR       (0xE80058A6)
   64: #define ADCWINLLB       (0xE80058A8)
   65: #define ADCWINLUB       (0xE80058AA)
   66: #define ADCMPBSR        (0xE80058AC)
   67: 
   68: #define ADANSC0         (0xE80058D4)
   69: #define ADGCTRGR        (0xE80058D9)
   70: 
   71: /* A/D Sampling state register ch.0-7 */
   72: #define ADSSTR(c)       (0xE80058E0 + c)
   73: 
   74: /*
   75:  * A/D converter interrupt number
   76: */
   77: #define INTNO_S12ADI0           247
   78: #define INTNO_S12GBADI0         248
   79: #define INTNO_S12GCADI0         249
   80: #define INTNO_S12ADCMPAI0       250
   81: #define INTNO_S12ADCMPBI0       251
   82: 
   83: #endif          /* __DEV_ADC_RZA2M_H__ */