gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      dev_adc_stm32l4.h
   16:  *      A/D converter device driver
   17:  *      System-dependent definition for STM32L4
   18:  */
   19: 
   20: #ifndef __DEV_ADC_STM32L4_H__
   21: #define __DEV_ADC_STM32L4_H__
   22: 
   23: #define DEV_ADC_UNITNM  (3)      /* Number of devive units */
   24: #define DEV_ADC_1       (0)   /* ADC1 */
   25: #define DEV_ADC_2       (1)   /* ADC2 */
   26: #define DEV_ADC_3       (2)   /* ADC3 */
   27: 
   28: /* NUmber of A/DC chanels */
   29: #define ADC_CH_NUM      (19)
   30: #define ADC_MAX_SQ      (16)
   31: 
   32: /*
   33:  * A/DC Clock source
   34:  */
   35: #define RCC_CCIPR_ADCSEL        0x30000000     // ADC Clock source
   36: 
   37: /*----------------------------------------------------------------------
   38:  * A/DC registers
   39:  */
   40: 
   41: /* A/DC common register */
   42: #define ADC_CSR         (0x50040300UL) // Common status register
   43: #define ADC_CCR         (0x50040308UL) // Common control register
   44: #define ADC_CDR         (0x5004030CUL) // Common regular register
   45: 
   46: /* Base address */
   47: #define ADC1_BASE       (0x50040000UL)
   48: #define ADC2_BASE       (0x50040100UL)
   49: #define ADC3_BASE       (0x50040200UL)
   50: 
   51: /* Register offset */
   52: #define ADCx_ISR        (0x00)         // Interrupt & status register
   53: #define ADCx_IER        (0x04)         // Interrupt enable register
   54: #define ADCx_CR         (0x08)         // Control register
   55: #define ADCx_CFGR       (0x0C)
   56: #define ADCx_CFGR2      (0x10)
   57: #define ADCx_SMPR1      (0x14)               // Sampling time register 1
   58: #define ADCx_SMPR2      (0x18)               // Sampling time register 2
   59: #define ADCx_TR1        (0x20)
   60: #define ADCx_TR2        (0x24)
   61: #define ADCx_TR3        (0x28)
   62: #define ADCx_SQR1       (0x30)                // Regular sequence register 1
   63: #define ADCx_SQR2       (0x34)                // Regular sequence register 2
   64: #define ADCx_SQR3       (0x38)                // Regular sequence register 3
   65: #define ADCx_SQR4       (0x3C)                // Regular sequence register 4
   66: #define ADCx_DR         (0x40)         // Regular data register
   67: #define ADCx_JSQR       (0x4C)
   68: #define ADCx_OFR1       (0x60)
   69: #define ADCx_OFR2       (0x64)
   70: #define ADCx_OFR3       (0x68)
   71: #define ADCx_OFR4       (0x6C)
   72: #define ADCx_JDR1       (0x80)
   73: #define ADCx_JDR2       (0x84)
   74: #define ADCx_JDR3       (0x88)
   75: #define ADCx_JDR4       (0x8C)
   76: #define ADCx_AWD2CR     (0xA0)
   77: #define ADCx_AWD3CR     (0xA4)
   78: #define ADCx_DIFSEL     (0xB0)
   79: #define ADCx_CALFACT    (0xB4)
   80: 
   81: #define ADC_ISR_ADRDY   (1<<0)            // ADC ready
   82: #define ADC_ISR_EOC     (1<<2)              // End of conversion
   83: #define ADC_ISR_EOS     (1<<3)              // End of regular sequence
   84: 
   85: #define ADC_IER_ADRDYIE (1<<0)          // ADC ready interrupt enable
   86: #define ADC_IER_EOCIE   (1<<2)            // End of conversion interrupt enable
   87: #define ADC_IER_OVRIE   (1<<4)            // Overrun interrupt enable
   88: 
   89: 
   90: #define ADC_CR_ADEN     (1<<0)              // ADC enable
   91: #define ADC_CR_ADDIS    (1<<1)             // ADC disable
   92: #define ADC_CR_ADSTART  (1<<2)           // ADC regular convert start
   93: #define ADC_CR_ADSTP    (1<<4)             // ADC regular convert stop
   94: #define ADC_CR_ADVREGEN (1<<28)         // ADC voltage regulator enabled
   95: #define ADC_CR_DEEPPWD  (1<<29)          // ADC deep powerdown enable
   96: #define ADC_CR_ADCAL    (1<<31)            // ADC calibration
   97: 
   98: /*
   99:  * A/D converter interrupt number
  100: */
  101: #define INTNO_INTADC1_2 18
  102: #define INTNO_INTADC3   47
  103: 
  104: #endif          /* __DEV_ADC_STM32L4_H__ */