gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.0
    4:  *
    5:  *    Copyright (C) 2020 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2020/10/21.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: 
   15: /*
   16:  *      dev_adc_m367.h
   17:  *      A/D converter device driver
   18:  *      System-dependent definition for TX03_M367
   19:  */
   20: 
   21: #ifndef __DEV_ADC_M367_H__
   22: #define __DEV_ADC_M367_H__
   23: 
   24: #define DEV_ADC_UNITNM  (2)      /* Number of devive units */
   25: #define DEV_ADC_UNIT0   (0)
   26: #define DEV_ADC_UNIT1   (1)
   27: 
   28: #define ADC_CH_NUM      (4)          /* NUmber of A/DC chanels */
   29: 
   30: /*
   31:  * ADC registers
   32:  */
   33: #define ADA_BASE        (0x40050000UL)
   34: #define ADB_BASE        (0x40051000UL)
   35: 
   36: #define ADxCLK          (0x00)          /* Clock setting register */
   37: 
   38: /* Mode register */
   39: #define ADxMOD0         (0x04)
   40: #define ADxMOD1         (0x08)
   41: #define ADxMOD2         (0x0C)
   42: #define ADxMOD3         (0x10)
   43: #define ADxMOD4         (0x14)
   44: #define ADxMOD5         (0x18)
   45: #define ADxMOD6         (0x1C)
   46: 
   47: /* Monitor interrupt setting register */
   48: #define ADxCMPCR0       (0x24)
   49: #define ADxCMPCR1       (0x28)
   50: 
   51: /* Conversion result comparison register */
   52: #define ADxCMP0         (0x2C)
   53: #define ADxCMP1         (0x30)
   54: 
   55: /* Conversion result storage register */
   56: #define ADxREG00        (0x34)
   57: #define ADxREG01        (0x38)
   58: #define ADxREG02        (0x3C)
   59: #define ADxREG03        (0x40)
   60: #define ADxREG04        (0x44)
   61: #define ADxREG05        (0x48)
   62: #define ADxREG06        (0x4C)
   63: #define ADxREG07        (0x50)
   64: 
   65: /* Register Bit definition */
   66: #define ADxMOD0_ADS     (1<<0)
   67: #define ADxMOD1_DACON   (1<<7)
   68: 
   69: /* Conversion mode (ADxMOD3) */
   70: #define ADMD_CHFIX_SINGLE       0x00  // MOD3.REPEAT = 0, MODE3.SCAN = 0
   71: #define ADMD_CHSCAN_SINGLE      0x01 // MOD3.REPEAT = 0, MODE3.SCAN = 1
   72: 
   73: /*
   74:  * A/D converter interrupt number
   75: */
   76: #define INTNO_INTADA    43
   77: #define INTNO_INTADB    47
   78: 
   79: #endif          /* __DEV_ADC_M367_H__ */