gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2020-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      i2c_stml4.h
   16:  *      I2C device driver
   17:  *      System-dependent definition for STM32L4
   18:  */
   19: 
   20: #ifndef __DEV_I2C_STM32L4_H__
   21: #define __DEV_I2C_STM32L4_H__
   22: 
   23: #define DEV_I2C_UNITNM          (3)     /* Number of devive units */
   24: #define DEV_I2C_1               (0)  /* I2C1 */
   25: #define DEV_I2C_2               (1)  /* I2C2 */
   26: #define DEV_I2C_3               (2)  /* I2C3 */
   27: 
   28: /* I2C device driver operating state */
   29: #define I2C_STS_START           0x0000
   30: #define I2C_STS_RESTART         0x0001
   31: #define I2C_STS_STOP            0x0003
   32: #define I2C_STS_SEND            0x0004
   33: #define I2C_STS_RECV            0x0005
   34: #define I2C_STS_TOP             0x8000
   35: 
   36: /*
   37:  * I2C Clock source
   38:  */
   39: #define RCC_CCIPR_I2CSEL        0x00003000     // I2C Clock source
   40: 
   41: /*----------------------------------------------------------------------
   42:  * I2C registers
   43:  */
   44: 
   45: /* Base address */
   46: #define I2C1_BASE               0x40005400
   47: #define I2C2_BASE               0x40005800
   48: #define I2C3_BASE               0x40005C00
   49: 
   50: /* Register offset */
   51: #define I2Cx_CR1                (0x00)                // Control register 1
   52: #define I2Cx_CR2                (0x04)                // Control register 2
   53: #define I2Cx_OAR1               (0x08)               // Own adress 1 register
   54: #define I2Cx_OAR2               (0x0C)               // Own adress 2 register
   55: #define I2Cx_TIMINGR            (0x10)            // Timing register
   56: #define I2Cx_TIMEOUTR           (0x14)           // Timeout register
   57: #define I2Cx_ISR                (0x18)                // Interrupt & status register
   58: #define I2Cx_ICR                (0x1C)                // Interrupt clear register
   59: #define I2Cx_PECR               (0x20)               // reserve
   60: #define I2Cx_RXDR               (0x24)               // Receive data register
   61: #define I2Cx_TXDR               (0x28)               // Transmission data register
   62: 
   63: #define I2C_CR1_PE              (1<<0)              // Peripheral enable
   64: #define I2C_CR1_TXIE            (1<<1)            // TX interrupt enable
   65: #define I2C_CR1_RXIE            (1<<2)            // RX interrupt enable
   66: #define I2C_CR1_NACKIE          (1<<4)          // NACK interrupt enable
   67: #define I2C_CR1_STOPIE          (1<<5)          // STOP interrupt enable
   68: #define I2C_CR1_TCIE            (1<<6)            // Transfer complete interrupt enable
   69: #define I2C_CR1_ERRIE           (1<<7)           // Error interrupt enable
   70: 
   71: #define I2C_CR2_RD_WRN          (1<<10)         // Communication direction
   72: #define I2C_CR2_START           (1<<13)          // START
   73: #define I2C_CR2_AUTOEND         (1<<25)                // Auto end mode
   74: 
   75: #define I2C_ISR_TXE             (1<<0)             // Transfer data empty
   76: #define I2C_ISR_TXIS            (1<<1)            // Transfer interrupt
   77: #define I2C_ISR_RXNE            (1<<2)            // Receive data not empty
   78: #define I2C_ISR_NACKF           (1<<4)           // NACK interrupt
   79: #define I2C_ISR_STOPF           (1<<5)           // STOP interrupt
   80: #define I2C_ISR_TC              (1<<6)              // Transfer complete interrupt
   81: #define I2C_ISR_TCR             (1<<7)             // Transfer complete & reload
   82: #define I2C_ISR_BUSY            (1<<15)           // Bus busy
   83: 
   84: #define I2C_ICR_ALL             (0x00003F38)       // All flag clear
   85: 
   86: /* 
   87:  * I2C interrupt number
   88:   */
   89: #define INTNO_I2C1_EV           31               // I2C1 event interrupt
   90: #define ININO_I2C1_ER           32               // I2C1 error interrupt
   91: 
   92: #define INTNO_I2C2_EV           33               // I2C2 event interrupt
   93: #define ININO_I2C2_ER           34               // I2C2 error interrupt
   94: 
   95: #define INTNO_I2C3_EV           72               // I2C3 event interrupt
   96: #define ININO_I2C3_ER           73               // I2C3 error interrupt
   97: 
   98: #endif          /* __DEV_I2C_STM32L4_H__ */