gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.0
    4:  *
    5:  *    Copyright (C) 2020 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2020/10/21.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      i2c_m367.h
   16:  *      I2C device driver
   17:  *      System-dependent definition for TX03_M367
   18:  */
   19: 
   20: #ifndef __DEV_I2C_M367_H__
   21: #define __DEV_I2C_M367_H__
   22: 
   23: #define DEV_I2C_UNITNM          (3)     /* Number of devive units */
   24: 
   25: /* I2C device driver operating state */
   26: #define I2C_STS_START           0x0000
   27: #define I2C_STS_RESTART         0x0001
   28: #define I2C_STS_STOP            0x0003
   29: #define I2C_STS_SEND            0x0004
   30: #define I2C_STS_RECV            0x0005
   31: #define I2C_STS_TOP             0x8000
   32: 
   33: /*----------------------------------------------------------------------
   34:  * I2C registers
   35:  */
   36: #define I2C0_BASE               (0x400E0000UL)
   37: #define I2C1_BASE               (0x400E0100UL)
   38: #define I2C2_BASE               (0x400E0200UL)
   39: 
   40: #define I2C_SBIxCR0             0x0000             /* RW Control register 0 */
   41: #define I2C_SBIxCR1             0x0004             /* RW Control register 1 */
   42: #define I2C_SBIxDBR             0x0008             /* RW Data buffer register */
   43: #define I2C_SBIxI2CAR           0x000C           /* RW I2C bus address register */
   44: #define I2C_SBIxCR2             0x0010             /* W  Control register 2 */
   45: #define I2C_SBIxSR              0x0010              /* R  Status register */
   46: #define I2C_SBIxBR0             0x0014             /* RW Baud rate register 0 */
   47: 
   48: /* Control register 0 - Bit definition */
   49: #define I2C_SBIxCR0_SBIEN       (1 << 7)      /* RW Serial bus interface enable */
   50: 
   51: /* Control register 1 - Bit definition */
   52: #define I2C_SBIxCR1_BC(n)       ((n) << 5)    /* RW Selection of transfer bit number */
   53: #define I2C_SBIxCR1_ACK         (1 << 4)       /* RW ACK */
   54: #define I2C_SBIxCR1_SCK(n)      ((n) << 0)   /* W  Output clock frequency selection */
   55: #define I2C_SBIxCR1_SWRMON      (1 << 0)     /* R  Software reset status moitor */
   56: 
   57: /* Control register 2 - Bit definition */
   58: #define I2C_SBIxCR2_MST         (1 << 7)       /* W Master / Slave mode Selection */
   59: #define I2C_SBIxCR2_TRX         (1 << 6)       /* W Send / Receive selection */
   60: #define I2C_SBIxCR2_BB          (1 << 5)        /* W Generation of start / stop condition */
   61: #define I2C_SBIxCR2_PIN         (1 << 4)       /* W INTSBIx Release interrupt request */
   62: #define I2C_SBIxCR2_SBIM(n)     ((n) << 2)  /* W Select operating mode of serial bus interface */
   63: #define I2C_SBIxCR2_SBIM_SIO    I2C_SBIxCR2_SBIM(1)
   64: #define I2C_SBIxCR2_SBIM_I2C    I2C_SBIxCR2_SBIM(2)
   65: #define I2C_SBIxCR2_SWRST(n)    ((n) << 0) /* W Occurrence of software reset */
   66: 
   67: /* Status register 0 Bit definition */
   68: #define I2C_SBIxSR_MST          (1 << 7)        /* R Master / slave selection */
   69: #define I2C_SBIxSR_TRX          (1 << 6)        /* R Transmitter / receiver selection status */
   70: #define I2C_SBIxSR_BB           (1 << 5) /* R I2C Bus state */
   71: #define I2C_SBIxSR_PIN          (1 << 4)        /* R INTSBIx Interrupt request status */
   72: #define I2C_SBIxSR_AL           (1 << 3) /* R Arbitration lost detection */
   73: #define I2C_SBIxSR_AAS          (1 << 2)        /* R Slave address match detection */
   74: #define I2C_SBIxSR_ADO          (1 << 1)        /* R General call detection */
   75: #define I2C_SBIxSR_LRB          (1 << 0)        /* R Last received bit */
   76: 
   77: /* Baud rate register 0 Bit definition */
   78: #define I2C_SBIxBR0_I2SBI       (1 << 6)      /* RW IDLE mode */
   79: /* 
   80:  * I2C interrupt number
   81:   */
   82: #define INTNO_INTSBI(n)         (26 + (n))     /* n=0～2 : I2C/SIO */
   83: 
   84: /*
   85:  * I2C/SIO setting value
   86:  */
   87: #define I2C_SBIxCR1_INIT        (      \
   88:                 I2C_SBIxCR1_BC(0) |   \
   89:                 I2C_SBIxCR1_ACK       )
   90: 
   91: #define I2C_SBIxCR2_START       (     \
   92:                 I2C_SBIxCR2_SBIM_I2C |        \
   93:                 I2C_SBIxCR2_MST |     \
   94:                 I2C_SBIxCR2_TRX |     \
   95:                 I2C_SBIxCR2_BB |      \
   96:                 I2C_SBIxCR2_PIN               )
   97: 
   98: #define I2C_SBIxCR2_RESTART     (   \
   99:                 I2C_SBIxCR2_SBIM_I2C |        \
  100:                 I2C_SBIxCR2_PIN               )
  101: 
  102: #define I2C_SBIxCR2_STOP        (      \
  103:                 I2C_SBIxCR2_SBIM_I2C |        \
  104:                 I2C_SBIxCR2_MST |     \
  105:                 I2C_SBIxCR2_TRX |     \
  106:                 I2C_SBIxCR2_PIN               )
  107: 
  108: #endif          /* __DEV_I2C_M367_H__ */