| mtkernel_3/device/ser/sysdepend/rx231/ser_rx231.h | bare source | permlink (0.01 seconds) |
1: /* 2: *---------------------------------------------------------------------- 3: * Device Driver for micro T-Kernel for μT-Kernel 3.0 4: * 5: * Copyright (C) 2020 by Ken Sakamura. 6: * This software is distributed under the T-License 2.2. 7: *---------------------------------------------------------------------- 8: * 9: * Released by TRON Forum(http://www.tron.org) at 2020/10/21. 10: * 11: *---------------------------------------------------------------------- 12: */ 13: 14: 15: /* 16: * ser_rx231.h 17: * Serial communication device driver 18: * System-dependent definition for RX231 19: */ 20: 21: #ifndef __DEV_SER_RX231_H__ 22: #define __DEV_SER_RX231_H__ 23: 24: #define DEV_SER_UNITNM (7) /* Number of devive channels */ 25: 26: /* 27: * UART registers 28: */ 29: 30: /* Base address for each channel */ 31: #define SCI0_BASE (0x8A000) 32: #define SCI1_BASE (0x8A020) 33: #define SCI5_BASE (0x8A0A0) 34: #define SCI6_BASE (0x8A0C0) 35: #define SCI8_BASE (0x8A100) 36: #define SCI9_BASE (0x8A120) 37: #define SCI12_BASE (0x8B300) 38: 39: /* Register offset */ 40: #define SCI_SMR (0x00000000) // Serial mode register 41: #define SCI_BRR (0x00000001) // Bit rate register 42: #define SCI_SCR (0x00000002) // Serial control register 43: #define SCI_SSR (0x00000004) // Serial status register 44: #define SCI_TDR (0x00000003) // Transmit data register 45: #define SCI_RDR (0x00000005) // Receive data register 46: #define SCI_SCMR (0x00000006) // Smart card mode register 47: #define SCI_SEMR (0x00000007) // Serial extended mode register 48: #define SCI_SPMR (0x0000000D) // SPI mode register 49: 50: /* SMR: Serial mode register */ 51: #define SCI_SMR_PCLK_01 (0x00) // Clock select bit 52: #define SCI_SMR_PCLK_04 (0x01) 53: #define SCI_SMR_PCLK_16 (0x02) 54: #define SCI_SMR_PCLK_64 (0x03) 55: #define SCI_SMR_CHR (0x40) // Character length bit 56: 57: /* SCR: Serial control register */ 58: #define SCI_SCR_TEIE (0x04) // Transmit end interrupt enable 59: #define SCI_SCR_RE (0x10) // Receive enable 60: #define SCI_SCR_TE (0x20) // Transmit enable 61: #define SCI_SCR_RIE (0x40) // Receive interrupt enable 62: #define SCI_SCR_TIE (0x80) // Transmit end interrupt enable 63: 64: #define SCI_SCR_INI (0x00) // SCR initial value 65: #define SCI_SCR_DEBUG (0x32) // SCR initial value when using debug 66: 67: /* SSR: Serial status register */ 68: #define SCI_SSR_TEND (0x04) // Transmit end 69: #define SCI_SSR_PER (0x08) // Parity error 70: #define SCI_SSR_FER (0x10) // Framing error 71: #define SCI_SSR_ORER (0x20) // Overrun error 72: #define SCI_SSR_RDRF (0x40) // Receive data full 73: #define SCI_SSR_TDRF (0x80) // Transmit data empty 74: 75: /* SEMR: Serial extended mode register */ 76: #define SCI_SEMR_ABCS (0x10) // Clock select */ 77: 78: /* SPMR: SPI mode register */ 79: #define SCI_SPMR_INI (0x00) // SPMR initial value 80: 81: /* 82: *UART interrupt number 83: */ 84: #define INTNO_SCI0_ERI 214 // Receive error interrupt 85: #define INTNO_SCI0_RXI 215 // Receive data full interrupt 86: #define INTNO_SCI0_TXI 216 // Transmit data empty interrupt 87: #define INTNO_SCI0_TEI 217 // Transmit end interrupt 88: 89: #define INTNO_SCI1_ERI 218 // Receive error interrupt 90: #define INTNO_SCI1_RXI 219 // Receive data full interrupt 91: #define INTNO_SCI1_TXI 220 // Transmit data empty interrupt 92: #define INTNO_SCI1_TEI 221 // Transmit end interrupt 93: 94: #define INTNO_SCI5_ERI 222 // Receive error interrupt 95: #define INTNO_SCI5_RXI 223 // Receive data full interrupt 96: #define INTNO_SCI5_TXI 224 // Transmit data empty interrupt 97: #define INTNO_SCI5_TEI 225 // Transmit end interrupt 98: 99: #define INTNO_SCI6_ERI 226 // Receive error interrupt 100: #define INTNO_SCI6_RXI 227 // Receive data full interrupt 101: #define INTNO_SCI6_TXI 228 // Transmit data empty interrupt 102: #define INTNO_SCI6_TEI 229 // Transmit end interrupt 103: 104: #define INTNO_SCI8_ERI 230 // Receive error interrupt 105: #define INTNO_SCI8_RXI 231 // Receive data full interrupt 106: #define INTNO_SCI8_TXI 232 // Transmit data empty interrupt 107: #define INTNO_SCI8_TEI 233 // Transmit end interrupt 108: 109: #define INTNO_SCI9_ERI 234 // Receive error interrupt 110: #define INTNO_SCI9_RXI 235 // Receive data full interrupt 111: #define INTNO_SCI9_TXI 236 // Transmit data empty interrupt 112: #define INTNO_SCI9_TEI 237 // Transmit end interrupt 113: 114: #define INTNO_SCI12_ERI 238 // Receive error interrupt 115: #define INTNO_SCI12_RXI 239 // Receive data full interrupt 116: #define INTNO_SCI12_TXI 240 // Transmit data empty interrupt 117: #define INTNO_SCI12_TEI 241 // Transmit end interrupt 118: 119: 120: #endif /* __DEV_SER_RX231_H__ */