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    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: 
   15: /*
   16:  *      ser_rza2m.h
   17:  *      Serial communication device driver
   18:  *      System-dependent definition for RZ/A2M
   19:  */
   20: 
   21: #ifndef __DEV_SER_RZA2M_H__
   22: #define __DEV_SER_RZA2M_H__
   23: 
   24: #define DEV_SER_UNITNM          (5)     /* Number of devive channels */
   25: 
   26: /*
   27:  * UART registers
   28:  */
   29: 
   30: /* Base address for each channel */
   31: #define SCI0_BASE               (0xE8007000)
   32: #define SCI1_BASE               (0xE8007800)
   33: #define SCI2_BASE               (0xE8008000)
   34: #define SCI3_BASE               (0xE8008800)
   35: #define SCI4_BASE               (0xE8009000)
   36: 
   37: /* Register offset */
   38: #define SCI_SMR                 (0x00000000)  // Serial mode register
   39: #define SCI_BRR                 (0x00000002)  // Bit rate register
   40: #define SCI_MDDR                (0x00000002)  // Modulation duty register
   41: #define SCI_SCR                 (0x00000004)  // Serial control register
   42: #define SCI_FTDR                (0x00000006)  // Transmit FIFO data register
   43: #define SCI_FSR                 (0x00000008)  // Serial status register
   44: #define SCI_FRDR                (0x0000000A)  // Receive FIFO data register
   45: #define SCI_FCR                 (0x0000000C)  // FIFO control register
   46: #define SCI_FDR                 (0x0000000E)  // FIFO data number register
   47: #define SCI_SPTR                (0x00000010)  // Serial port register
   48: #define SCI_LSR                 (0x00000012)  // Line status register
   49: #define SCI_SEMR                (0x00000014)  // Serial extended mode register
   50: #define SCI_FTCR                (0x00000016)  // FIFO trigger control
   51: 
   52: /*  SMR: Serial mode register */
   53: #define SCI_SMR_CKS             (0x0003)   // Clock select bit
   54: #define SCI_SMR_CHR             (0x0040)   // Character length bit
   55: 
   56: /* SCR: Serial control register */
   57: #define SCI_SCR_TEIE            (0x0004)  // Transmit end interrupt enable
   58: #define SCI_SCR_REIE            (0x0008)  // Receive error interrupt enable
   59: #define SCI_SCR_RE              (0x0010)    // Receive enable
   60: #define SCI_SCR_TE              (0x0020)    // Transmit enable
   61: #define SCI_SCR_RIE             (0x0040)   // Receive interrupt enable
   62: #define SCI_SCR_TIE             (0x0080)   // Transmit interrupt enable
   63: 
   64: #define SCI_SCR_INI             (0x0000)   // SCR initial value
   65: #define SCI_SCR_DEBUG           (0x0030) // SCR initial value when using debug
   66: 
   67: /* FSR: Serial status register */
   68: #define SCI_FSR_DR              (0x0001)    // Receive data ready
   69: #define SCI_FSR_RDF             (0x0002)   // Receive FIFO data full
   70: #define SCI_FSR_PER             (0x0004)   // Parity error
   71: #define SCI_FSR_FER             (0x0008)   // Framing error
   72: #define SCI_FSR_BRK             (0x0010)   // Break detection
   73: #define SCI_FSR_TDFE            (0x0020)  // Transmit FIFO data empty
   74: #define SCI_FSR_TEND            (0x0040)  // Transmit end
   75: #define SCI_FSR_ER              (0x0080)    // Receive error
   76: 
   77: /* SPTR: Serial port register */
   78: #define SCI_SPTR_INI            (0x0003)  // SPTR  initial value
   79: 
   80: /* LSR: Line status register */
   81: #define SCI_LSR_ORER            (0x0001)  // Overrun error
   82: 
   83: /* SEMR: Serial extended mode register */
   84: #define SCI_SEMR_ABCS           (0x01)           // Clock select */
   85: 
   86: /* FCR: FIFO control register */
   87: #define SCI_FCR_RFRST           (0x0002) // Receive FIFO Reset
   88: #define SCI_FCR_TFRST           (0x0004) // Transmit FIFO Reset
   89: 
   90: #define SCI_FCR_INI             (0x0600)   // FCR initial value
   91: 
   92: /* FTCR: FIFO trigger control*/
   93: #define SCI_FTCR_INI            (0x8390)  // SPTR initial value (RTRGS=1, RFTC=1, TTRGS=1, TFTC=16)
   94: 
   95: /*
   96:  *UART interrupt number
   97:  */
   98: #define INTNO_SCI0_ERI          297             // Receive error interrupt
   99: #define INTNO_SCI0_RXI          298             // Receive data full interrupt
  100: #define INTNO_SCI0_TXI          299             // Transmit data empty interrupt
  101: #define INTNO_SCI0_TEI          300             // Transmit end interrupt
  102: 
  103: #define INTNO_SCI1_ERI          303             // Receive error interrupt
  104: #define INTNO_SCI1_RXI          304             // Receive data full interrupt
  105: #define INTNO_SCI1_TXI          305             // Transmit data empty interrupt
  106: #define INTNO_SCI1_TEI          306             // Transmit end interrupt
  107: 
  108: #define INTNO_SCI2_ERI          309             // Receive error interrupt
  109: #define INTNO_SCI2_RXI          310             // Receive data full interrupt
  110: #define INTNO_SCI2_TXI          311             // Transmit data empty interrupt
  111: #define INTNO_SCI2_TEI          312             // Transmit end interrupt
  112: 
  113: #define INTNO_SCI3_ERI          315             // Receive error interrupt
  114: #define INTNO_SCI3_RXI          316             // Receive data full interrupt
  115: #define INTNO_SCI3_TXI          317             // Transmit data empty interrupt
  116: #define INTNO_SCI3_TEI          318             // Transmit end interrupt
  117: 
  118: #define INTNO_SCI4_ERI          321             // Receive error interrupt
  119: #define INTNO_SCI4_RXI          322             // Receive data full interrupt
  120: #define INTNO_SCI4_TXI          323             // Transmit data empty interrupt
  121: #define INTNO_SCI4_TEI          324             // Transmit end interrupt
  122: 
  123: 
  124: #endif          /* __DEV_SER_RZA2M_H__ */