gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2020-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: 
   15: /*
   16:  *      ser_stm32l4.h
   17:  *      Serial communication device driver
   18:  *      System-dependent definition for STM32L4
   19:  */
   20: 
   21: #ifndef __DEV_SER_STM32L4_H__
   22: #define __DEV_SER_STM32L4_H__
   23: 
   24: #define DEV_SER_UNITNM  (3)      /* Number of devive channels */
   25: #define DEV_SER_UNIT0   (0)       /* Ch.0 - USART1 */
   26: #define DEV_SER_UNIT1   (1)       /* Ch.1 - USART2 */
   27: #define DEV_SER_UNIT2   (2)       /* Ch.2 - USART3 */
   28: 
   29: /*
   30:  * USART registers
   31:  */
   32: 
   33: /* Base address for each channel */
   34: #define USART1_BASE     (0x40013800UL)
   35: #define USART2_BASE     (0x40004400UL)
   36: #define USART3_BASE     (0x40004800UL)
   37: 
   38: /* Register offset */
   39: #define USARTx_CR1      (0x0000)     /* Control register 1 */
   40: #define USARTx_CR2      (0x0004)     /* Control register 2 */
   41: #define USARTx_CR3      (0x0008)     /* Control register 3 */
   42: #define USARTx_BRR      (0x000C)     /* baud rate register */
   43: #define USARTx_GTPR     (0x0010)    /* Guard time and Priscaler register */
   44: #define USARTx_RTOR     (0x0014)    /* Receiver timeout register */
   45: #define USARTx_RQR      (0x0018)     /* Request register */
   46: #define USARTx_ISR      (0x001C)     /* Interrupts and status register */
   47: #define USARTx_ICR      (0x0020)     /* Interrupt flag clear register */
   48: #define USARTx_RDR      (0x0024)     /* Received data register */
   49: #define USARTx_TDR      (0x0028)     /* Transmission data register */
   50: 
   51: /* Register bit definition */
   52: #define USART_CR1_UE            (1<<0)    /* RW USART enable */
   53: #define USART_CR1_UESM          (1<<1)  /* RW USART enable in STOP mode */
   54: #define USART_CR1_RE            (1<<2)    /* RW Receiver enable */
   55: #define USART_CR1_TE            (1<<3)    /* RW Transmitter enable */
   56: #define USART_CR1_IDLEIE        (1<<4) /* RW IDLE interrupt enable */
   57: #define USART_CR1_RXNEIE        (1<<5) /* RW RXNE interrupt enable */
   58: #define USART_CR1_TCIE          (1<<6)  /* RW TCOE interrupt enable */
   59: #define USART_CR1_TXEIE         (1<<7) /* RW TXE interrupt enable */
   60: #define USART_CR1_PEIE          (1<<8)  /* RW PE interrupt enable */
   61: #define USART_CR1_PS            (1<<9)    /* RW Parity selection */
   62: #define USART_CR1_PCE           (1<<10)  /* RW Parity control enable */
   63: #define USART_CR1_WAKE          (1<<11) /* RW Receive wakeup method */
   64: #define USART_CR1_M0            (1<<12)   /* RW Word length 0 */
   65: #define USART_CR1_MME           (1<<13)  /* RW Mute mode enable */
   66: #define USART_CR1_CMIE          (1<<14) /* RW Character match interrupt enable */
   67: #define USART_CR1_OVER8         (1<<15)        /* RW Oversampling mode */
   68: #define USART_CR1_RTOIE         (1<<26)        /* RW Receiver timeout interrupt enable */
   69: #define USART_CR1_EOBIE         (1<<27)        /* RW End of Block interrupt enabled */
   70: #define USART_CR1_M1            (1<<28)   /* RW Word length 1 */
   71: 
   72: #define USART_CR2_STOP          (3<<12) /* RW Stop-bit */
   73: 
   74: #define USART_CR3_RTSE          (1<<8)  /* RTS enable */
   75: #define USART_CR3_CTSE          (1<<9)  /* CTS enable */
   76: 
   77: #define USART_RQR_SBKRQ         (1<<1) /* Break send request */
   78: 
   79: #define USART_ISR_PE            (1<<0)    /* R Parity error */
   80: #define USART_ISR_FE            (1<<1)    /* R Framing error */
   81: #define USART_ISR_NF            (1<<2)    /* R Start bit noise detection */
   82: #define USART_ISR_ORE           (1<<3)   /* R Overrun error */
   83: #define USART_ISR_IDLE          (1<<4)  /* R Idle line detection */
   84: #define USART_ISR_RXNE          (1<<5)  /* R Received data register not empty */
   85: #define USART_ISR_TC            (1<<6)    /* R Transmission completely */
   86: #define USART_ISR_TXE           (1<<7)   /* R Transmission data register empty */
   87: #define USART_ISR_LBDF          (1<<8)  /* R LIN break detection */
   88: #define USART_ISR_CTSIF         (1<<9) /* R CTS interrupt */
   89: #define USART_ISR_CTS           (1<<10)  /* R CTS flag */
   90: #define USART_ISR_RTOF          (1<<11) /* R Receiver timeout */
   91: #define USART_ISR_EOBF          (1<<12) /* R End of block */
   92: #define USART_ISR_ABRE          (1<<14) /* R Automatic baud rate error */
   93: #define USART_ISR_ABRF          (1<<15) /* R Automatic baud rate flag */
   94: #define USART_ISR_BUSY          (1<<16) /* R Busy flag */
   95: #define USART_ISR_CMF           (1<<17)  /* R Character match flag */
   96: #define USART_ISR_SBKF          (1<<18) /* R Break transmission flag */
   97: #define USART_ISR_RWU           (1<<6)   /* R Receiver mute mode flag */
   98: #define USART_ISR_WUF           (1<<6)   /* R Wakeup flag */
   99: #define USART_ISR_TEACK         (1<<6) /* R Transmission ACK flag */
  100: #define USART_ISR_REACK         (1<<6) /* R Receive ACK flag */
  101: #define USART_ISR_ERR           (USART_ISR_PE|USART_ISR_FE|USART_ISR_NF|USART_ISR_ORE)
  102: 
  103: #define USART_ICR_PECF          (1<<0)
  104: #define USART_ICR_FECF          (1<<1)
  105: #define USART_ICR_NCF           (1<<2)
  106: #define USART_ICR_ORECF         (1<<3)
  107: #define USART_ICR_IDLECF        (1<<4)
  108: #define USART_ICR_TCCF          (1<<6)
  109: #define USART_ICR_TCBGTCF       (1<<7)
  110: #define USART_ICR_LBDCF         (1<<8)
  111: #define USART_ICR_CTSCF         (1<<9)
  112: #define USART_ICR_RTOCF         (1<<11)
  113: #define USART_ICR_EOBCF         (1<<12)
  114: #define USART_ICR_CMCF          (1<<17)
  115: #define USART_ICR_WUCF          (1<<20)
  116: #define USART_ICR_ALL           (0x00121BDF)
  117: 
  118: /*Initial register value when using debug */
  119: #define USART_CR1_DEBUG         0x0000000D     /* USART enable, 8bit, Non parity */
  120: #define USART_CR2_DEBUG         0              /* Stop bit 1 */
  121: #define USART_CR3_DEBUG         0              /* No hard flow control */
  122: 
  123: 
  124: /* USART interrupt number */
  125: #define INTNO_USART1            37
  126: #define INTNO_USART2            38
  127: #define INTNO_USART3            39
  128: 
  129: #endif          /* __DEV_SER_STM32L4_H__ */