gonzui: mtkernel_3/device/ser/sysdepend/tx03_m367/ser

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    Device Driver for micro T-Kernel for μT-Kernel 3.0
    4:  *
    5:  *    Copyright (C) 2020 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2020/10/21.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: 
   15: /*
   16:  *      ser_m367.h
   17:  *      Serial communication device driver
   18:  *      System-dependent definition for TX03_M367
   19:  */
   20: 
   21: #ifndef __DEV_SER_M367_H__
   22: #define __DEV_SER_M367_H__
   23: 
   24: #define DEV_SER_UNITNM          (2)     /* Number of devive channels */
   25: #define DEV_SER_UNIT0           (0)
   26: #define DEV_SER_UNIT1           (1)
   27: 
   28: /*
   29:  * UART registers
   30:  */
   31: 
   32: /* Base address for each channel */
   33: #define UART4_BASE              (0x40048000UL)      /* UART modem */
   34: #define UART5_BASE              (0x40049000UL)
   35: 
   36: /* UART modem */
   37: #define UARTxDR                 (0x0000)      /* Data register */
   38: #define UARTxRSR                (0x0004)     /* Receive status register */
   39: #define UARTxECR                (0x0004)     /* Error clear register */
   40: #define UARTxFR                 (0x0018)      /* Flag register */
   41: #define UARTxILPR               (0x0020)    /* IrDA low-power counter */
   42: #define UARTxIBDR               (0x0024)    /* Integer baud rate register */
   43: #define UARTxFBDR               (0x0028)    /* Fractional baud rate register */
   44: #define UARTxLCR_H              (0x002C)   /* Line control register */
   45: #define UARTxCR                 (0x0030)      /* Control register */
   46: #define UARTxIFLS               (0x0034)    /* Interrupt FIFO level select register */
   47: #define UARTxIMSC               (0x0038)    /* Interrupt mask set/clear register */
   48: #define UARTxRIS                (0x003C)     /* Raw interrupt status register */
   49: #define UARTxMIS                (0x0040)     /* Masked interrupt status register */
   50: #define UARTxICR                (0x0044)     /* Interrupt clear register */
   51: #define UARTxDMACR              (0x0048)   /* DMA control register */
   52: 
   53: #define UARTxDR_OE              (1 << 11)   /* R Overrun error */
   54: #define UARTxDR_BE              (1 << 10)   /* R Break error */
   55: #define UARTxDR_PE              (1 << 9)    /* R Parity error */
   56: #define UARTxDR_FE              (1 << 8)    /* R Framing error */
   57: #define UARTxDR_DATA            (0xff)            /* RW Send / receive data */
   58: 
   59: #define UARTxRSR_OE             (1 << 3)   /* R Overrun error */
   60: #define UARTxRSR_BE             (1 << 2)   /* R Break error */
   61: #define UARTxRSR_PE             (1 << 1)   /* R Parity error */
   62: #define UARTxRSR_FE             (1 << 0)   /* R Framing error */
   63: 
   64: #define UARTxFR_RI              (1 << 8)    /* R Link indicator */
   65: #define UARTxFR_TXFE            (1 << 7)  /* R Send empty */
   66: #define UARTxFR_RXFF            (1 << 6)  /* R Receive full */
   67: #define UARTxFR_TXFF            (1 << 5)  /* R Send full */
   68: #define UARTxFR_RXFE            (1 << 4)  /* R Receive empty */
   69: #define UARTxFR_BUSY            (1 << 3)  /* R UART busy */
   70: #define UARTxFR_DCD             (1 << 2)   /* R Data carrier detect */
   71: #define UARTxFR_DSR             (1 << 1)   /* R Data set ready */
   72: #define UARTxFR_CTS             (1 << 0)   /* R Clear to send */
   73: 
   74: #define UARTxLCR_H_SPS          (1 << 7)        /* RW Stick parity selection */
   75: #define UARTxLCR_H_WLEN(n)      (((n)-5) << 5)       /* RW Word length (5～8bit) */
   76: #define UARTxLCR_H_FEN          (1 << 4)        /* RW Enable FIFO */
   77: #define UARTxLCR_H_STP2         (1 << 3)       /* RW Stop bit selection */
   78: #define UARTxLCR_H_EPS          (1 << 2)        /* RW Even parity selection */
   79: #define UARTxLCR_H_PEN          (1 << 1)        /* RW Parity enable */
   80: #define UARTxLCR_H_BRK          (1 << 0)        /* RW Send break */
   81: 
   82: #define UARTxCR_CTSEN           (1 << 15)        /* RW CTS Hardware flow control enable */
   83: #define UARTxCR_RTSEN           (1 << 14)        /* RW RTS Hardware flow control enable */
   84: #define UARTxCR_RTS             (1 << 11)  /* RW Request to send(RTS) */
   85: #define UARTxCR_DTR             (1 << 10)  /* RW Ready to send data (DTS) */
   86: #define UARTxCR_RXE             (1 << 9)   /* RW Receive enable */
   87: #define UARTxCR_TXE             (1 << 8)   /* RW Send enable */
   88: #define UARTxCR_SIRLP           (1 << 2) /* RW IrDA  SIR Low power mode */
   89: #define UARTxCR_SIREN           (1 << 1) /* RW SIR Enable */
   90: #define UARTxCR_UARTEN          (1 << 0)        /* RW UART Enable */
   91: 
   92: #define UARTxIFLS_RXIFLSEL(n)   ((n) << 3)        /* RW Receive interrupt FIFO Level */
   93: #define UARTxIFLS_TXIFLSEL(n)   ((n) << 0)        /* RW Transmission interrupt FIFO Level */
   94: #define UARTxIFLS_1_8           0                /* FIFO 1/8 */
   95: #define UARTxIFLS_1_4           1                /* FIFO 1/4 */
   96: #define UARTxIFLS_1_2           2                /* FIFO 1/2 */
   97: #define UARTxIFLS_3_4           3                /* FIFO 3/4 */
   98: #define UARTxIFLS_7_8           4                /* FIFO 7/8 */
   99: 
  100: #define UARTxIFLS_RXINI         UARTxIFLS_1_2  // Receive FIFO 1/2
  101: #define UARTxIFLS_TXINI         UARTxIFLS_1_4  // Send FIFO 1/4
  102: 
  103: #define UARTxINT_OE             (1 << 10)  /* RW Overrun error interrupt */
  104: #define UARTxINT_BE             (1 << 9)   /* RW Break error interrupt */
  105: #define UARTxINT_PE             (1 << 8)   /* RW Parity error interrupt */
  106: #define UARTxINT_FE             (1 << 7)   /* RW Framing error interrupt */
  107: #define UARTxINT_RT             (1 << 6)   /* RW Receive timeout interrupt */
  108: #define UARTxINT_TX             (1 << 5)   /* RW Transmission interrupt */
  109: #define UARTxINT_RX             (1 << 4)   /* RW Receive interrupt */
  110: #define UARTxINT_DSR            (1 << 3)  /* RW DSR Modem interrupt */
  111: #define UARTxINT_DCD            (1 << 2)  /* RW DCD Modem interrupt */
  112: #define UARTxINT_CTS            (1 << 1)  /* RW CTS Modem interrupt */
  113: #define UARTxINT_RI             (1 << 0)   /* RW RIN Modem interrupt */
  114: 
  115: #define UARTxINT_ALL            (0x000007FF)
  116: #define UARTxINT_COM            (UARTxINT_OE|UARTxINT_BE|UARTxINT_PE|UARTxINT_FE| \
  117:                                         UARTxINT_RT|UARTxINT_TX|UARTxINT_RX)
  118: 
  119: #define UARTxDMACR_DMAONERR     (1 << 2)    /* RW DMA On error */
  120: #define UARTxDMACR_TXDMAE       (1 << 1)      /* RW Transmission DMA Enable */
  121: #define UARTxDMACR_RXDMAE       (1 << 0)      /* RW Receive DMA Enable */
  122: 
  123: /* UART interrupt number */
  124: #define INTNO_UART0             24
  125: #define INTNO_UART1             25
  126: 
  127: #endif          /* __DEV_SER_M367_H__ */