1: /*
2: *----------------------------------------------------------------------
3: * micro T-Kernel 3.00.05
4: *
5: * Copyright (C) 2006-2021 by Ken Sakamura.
6: * This software is distributed under the T-License 2.2.
7: *----------------------------------------------------------------------
8: *
9: * Released by TRON Forum(http://www.tron.org) at 2021/11.
10: *
11: *----------------------------------------------------------------------
12: */
13:
14: /*
15: * tkernel_map.ld
16: * micro T-Kernel linker script for RZ/A2M IoT-Engine
17: */
18:
19: MEMORY {
20: SERIAL_FLASH (r) : ORIGIN = 0x20000000, LENGTH = 0x02000000
21: BACKUP_RAM (rw) : ORIGIN = 0x80000000, LENGTH = 0x00020000
22: CACHED_RAM (rw) : ORIGIN = 0x80020000, LENGTH = 0x002e0000
23: UNCACHED_RAM (rw) : ORIGIN = 0x80300000, LENGTH = 0x000fc000
24: TTB_RAM (rw) : ORIGIN = 0x803fc000, LENGTH = 0x00004000
25: }
26:
27: SECTIONS
28: {
29: .text : ALIGN(0x20) {
30: __vector_start = .;
31: *(VECTOR_TABLE)
32: __vector_end = .;
33: __start = .;
34: * (RESET_HANDLER)
35: * (EXC_ENTRY)
36: * (INIT_TTB)
37: * (IRQ_FIQ_HANDLER)
38: * (OTHER_HANDLER)
39: * (.text .text.*)
40: * (.rodata .rodata.*)
41: } > CACHED_RAM
42:
43: .data : ALIGN(0x20) {
44: * (.data .data.*)
45: . = ALIGN(0x10);
46: } > CACHED_RAM
47:
48: .noload (NOLOAD) : ALIGN(0x20) {
49: *(.noinit)
50: } > CACHED_RAM
51:
52: .bss (NOLOAD) : ALIGN(0x20) {
53: * (.EIT_VecTable)
54: . = ALIGN(0x10);
55: * (.bss .bss.*)
56: * (COMMON)
57: . = ALIGN( 0x20 );
58: } > CACHED_RAM
59:
60: .stack (NOLOAD) : ALIGN(0x20) {
61: __tmp_stack_end = .;
62: * (.tmp_stack_section)
63: __tmp_stack_start = .;
64:
65: __fiq_stack_end = .;
66: * (.fiq_stack_section)
67: __fiq_stack_start = .;
68:
69: __irq_stack_end = .;
70: * (.irq_stack_section)
71: __irq_stack_start = .;
72:
73: __und_stack_end = .;
74: * (.und_stack_section)
75: __und_stack_start = .;
76:
77: __abt_stack_end = .;
78: * (.abt_stack_section)
79: __abt_stack_start = .;
80:
81: _HeapStart = .; /* start of heap area */
82: } > CACHED_RAM
83: _HeapEnd = ORIGIN(CACHED_RAM) + LENGTH(CACHED_RAM); /* end of heap area */
84:
85: .uncached_RAM (NOLOAD) : {
86: } > UNCACHED_RAM
87:
88: .ttb (NOLOAD) : {
89: __ttb_area_top = .;
90: . += 0x00004000;
91: __ttb_area_bottom = .;
92: } > TTB_RAM
93:
94: _text_load = ABSOLUTE( LOADADDR(.text) ); /* load base address of .text section */
95: _text_start = ABSOLUTE( ADDR(.text) ); /* execute base address of .text section */
96: _text_size = SIZEOF(.text);
97: _text_end = _text_start + _text_size;
98:
99: _data_org = ABSOLUTE( LOADADDR(.data) ); /* load base address of .data section */
100: _data_start = ABSOLUTE( ADDR(.data) ); /* execute base address of .data section */
101: _data_size = SIZEOF(.data);
102: _data_end = _data_start + _data_size;
103:
104: _bss_start = ABSOLUTE( ADDR(.bss) ); /* execute base address of .bss section */
105: _bss_size = SIZEOF(.bss);
106: _bss_end = _bss_start + _bss_size;
107: }