1: /*
2: *----------------------------------------------------------------------
3: * micro T-Kernel 3.00.05
4: *
5: * Copyright (C) 2006-2021 by Ken Sakamura.
6: * This software is distributed under the T-License 2.2.
7: *----------------------------------------------------------------------
8: *
9: * Released by TRON Forum(http://www.tron.org) at 2021/11.
10: *
11: *----------------------------------------------------------------------
12: */
13:
14: /*
15: * tkernel_map.ld
16: * micro T-Kernel linker script for RZ/A2M IoT-Engine
17: */
18:
19: MEMORY {
20: SERIAL_FLASH (r) : ORIGIN = 0x20000000, LENGTH = 0x02000000
21: BACKUP_RAM (rw) : ORIGIN = 0x80000000, LENGTH = 0x00020000
22: CACHED_RAM (rw) : ORIGIN = 0x80020000, LENGTH = 0x002e0000
23: UNCACHED_RAM (rw) : ORIGIN = 0x80300000, LENGTH = 0x000fc000
24: TTB_RAM (rw) : ORIGIN = 0x803fc000, LENGTH = 0x00004000
25: }
26:
27: SECTIONS
28: {
29: .sf_text : ALIGN(0x20) {
30: __sf_vector_start = .;
31: *(SF_VECTOR_TABLE)
32: __sf_vector_end = .;
33: __sf_start = .;
34: * (SF_RESET_HANDLER)
35: } > SERIAL_FLASH
36:
37: .text : ALIGN(0x20) {
38: __vector_start = .;
39: *(VECTOR_TABLE)
40: __vector_end = .;
41: __start = .;
42: * (RESET_HANDLER)
43: * (EXC_ENTRY)
44: * (INIT_TTB)
45: * (IRQ_FIQ_HANDLER)
46: * (OTHER_HANDLER)
47: * (.text .text.*)
48: * (.rodata .rodata.*)
49: } > CACHED_RAM AT > SERIAL_FLASH
50:
51: .data : ALIGN(0x20) {
52: * (.data .data.*)
53: . = ALIGN(0x10);
54: } > CACHED_RAM AT > SERIAL_FLASH
55:
56: .noload (NOLOAD) : ALIGN(0x20) {
57: *(.noinit)
58: } > CACHED_RAM
59:
60: .bss (NOLOAD) : ALIGN(0x20) {
61: * (.EIT_VecTable)
62: . = ALIGN(0x10);
63: * (.bss .bss.*)
64: * (COMMON)
65: . = ALIGN( 0x20 );
66: } > CACHED_RAM
67:
68: .stack (NOLOAD) : ALIGN(0x20) {
69: __tmp_stack_end = .;
70: * (.tmp_stack_section)
71: __tmp_stack_start = .;
72:
73: __fiq_stack_end = .;
74: * (.fiq_stack_section)
75: __fiq_stack_start = .;
76:
77: __irq_stack_end = .;
78: * (.irq_stack_section)
79: __irq_stack_start = .;
80:
81: __und_stack_end = .;
82: * (.und_stack_section)
83: __und_stack_start = .;
84:
85: __abt_stack_end = .;
86: * (.abt_stack_section)
87: __abt_stack_start = .;
88:
89: _HeapStart = .; /* start of heap area */
90: } > CACHED_RAM
91: _HeapEnd = ORIGIN(CACHED_RAM) + LENGTH(CACHED_RAM); /* end of heap area */
92:
93: .uncached_RAM (NOLOAD) : {
94: } > UNCACHED_RAM
95:
96: .ttb (NOLOAD) : {
97: __ttb_area_top = .;
98: . += 0x00004000;
99: __ttb_area_bottom = .;
100: } > TTB_RAM
101:
102: _text_load = ABSOLUTE( LOADADDR(.text) ); /* load base address of .text section */
103: _text_start = ABSOLUTE( ADDR(.text) ); /* execute base address of .text section */
104: _text_size = SIZEOF(.text);
105: _text_end = _text_start + _text_size;
106:
107: _data_org = ABSOLUTE( LOADADDR(.data) ); /* load base address of .data section */
108: _data_start = ABSOLUTE( ADDR(.data) ); /* execute base address of .data section */
109: _data_size = SIZEOF(.data);
110: _data_end = _data_start + _data_size;
111:
112: _bss_start = ABSOLUTE( ADDR(.bss) ); /* execute base address of .bss section */
113: _bss_size = SIZEOF(.bss);
114: _bss_end = _bss_start + _bss_size;
115: }