gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: /*
   14:  *      profile.h
   15:  *
   16:  *      Service Profile (ARMv7-A core depended)
   17:  */
   18: 
   19: #ifndef __SYS_PROFILE_CORE_H__
   20: #define __SYS_PROFILE_CORE_H__
   21: 
   22: #define TK_ALLOW_MISALIGN       (ALLOW_MISALIGN)      /* Memory misalign access is permitted */
   23: #define TK_BIGENDIAN            (BIGENDIAN)               /* Is Big Endian (Must be defined) */
   24: 
   25: /*
   26:  * FPU and co-processors
   27:  */
   28: #define TK_SUPPORT_FPU          FALSE                   /* Support of FPU */
   29: #define TK_SUPPORT_COP0         FALSE                  /* Support of co-processor-0 */
   30: #define TK_SUPPORT_COP1         FALSE                  /* Support of co-processor-1 */
   31: #define TK_SUPPORT_COP2         FALSE                  /* Support of co-processor-2 */
   32: #define TK_SUPPORT_COP3         FALSE                  /* Support of co-processor-3 */
   33: 
   34: /*
   35:  * low-level function
   36:  */
   37: #define TK_SUPPORT_REGOPS       TRUE                  /* Support of get/set register operation */
   38: #define TK_SUPPORT_ASM          FALSE                   /* Support of assembly language function entry/exit */
   39: 
   40: /*
   41:  * Interrupt
   42:  */
   43: #define TK_SUPPORT_INTCTRL      TRUE                 /* Support of interrupt controller management. */
   44: #define TK_HAS_ENAINTLEVEL      TRUE                         /* Can specify interrupt priority level */
   45: #define TK_SUPPORT_CPUINTLEVEL  FALSE                    /* Support of get/set of CPU interrupt mask level */
   46: #define TK_SUPPORT_CTRLINTLEVEL TRUE                    /* Support of get/set of interrupt controller interrupt mask level */
   47: #define TK_SUPPORT_INTMODE      TRUE                 /* Supoprt of interrupt mode setting */
   48: 
   49: /*
   50:  * Cache control
   51:  */
   52: #define TK_SUPPORT_CACHECTRL    FALSE                      /* support of cache control */
   53: #define TK_SUPPORT_WBCACHE      FALSE                        /* Support of write-back cache */
   54: #define TK_SUPPORT_WTCACHE      FALSE                        /* Support of write-through cache */
   55: 
   56: /*
   57:  * Real memory protection level of TA_RNGn (0..3)
   58:  */
   59: #define TK_MEM_RNG0             0
   60: #define TK_MEM_RNG1             0
   61: #define TK_MEM_RNG2             0
   62: #define TK_MEM_RNG3             0
   63: 
   64: /*
   65:  * Device Support
   66:  */
   67: #define TK_SUPPORT_MICROWAIT    TRUE                       /* Support of micro wait */
   68: 
   69: #endif /* __SYS_PROFILE_CORE_H__ */