gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      sysdef_depend.h
   16:  *
   17:  *      System dependencies definition (ARMv7-A core depended)
   18:  *      Included also from assembler program.
   19:  */
   20: 
   21: #ifndef __SYS_SYSDEF_DEPEND_CORE_H__
   22: #define __SYS_SYSDEF_DEPEND_CORE_H__
   23: 
   24: /* ------------------------------------------------------------------------ */
   25: /*
   26:  * Program Status Register (PSR)
   27:  */
   28: #define PSR_N           0x80000000       /* conditional flag  negative */
   29: #define PSR_Z           0x40000000       /*                 zero */
   30: #define PSR_C           0x20000000       /*                 carry */
   31: #define PSR_V           0x10000000       /*                 overflow */
   32: #define PSR_Q           0x08000000       /* Sticky overflow */
   33: #define PSR_GE          0x000f0000      /* SIMD >= flag  */
   34: 
   35: #define PSR_J           0x01000000       /* Jazelle mode */
   36: #define PSR_IT          0x0600fc00      /* Thumb If-Then state */
   37: #define PSR_E           0x00000200       /* data endian */
   38: #define PSR_A           0x00000100       /* disable asynchronous abort */
   39: #define PSR_I           0x00000080       /* disable interrupt(IRQ) */
   40: #define PSR_F           0x00000040       /* disable fast interrupt(FIQ) */
   41: #define PSR_T           0x00000020       /* Thumb mode */
   42: 
   43: #define PSR_M(n)        ( n )          /* processor mode 0-31 */
   44: #define PSR_USR         PSR_M(16)      /* user mode */
   45: #define PSR_FIQ         PSR_M(17)      /* fast interrupt(FIQ) mode */
   46: #define PSR_IRQ         PSR_M(18)      /* interrupt (IRQ) mode */
   47: #define PSR_SVC         PSR_M(19)      /* supervisor mode */
   48: #define PSR_ABT         PSR_M(23)      /* abort mode */
   49: #define PSR_UND         PSR_M(27)      /* undefined instruction mode */
   50: #define PSR_SYS         PSR_M(31)      /* system mode */
   51: 
   52: #define PSR_DI          ( PSR_I|PSR_A ) /* disable (ordinary) interrupt */
   53: 
   54: /*
   55:  * CP15 System Control Register (SCTLR)
   56:  */
   57: #define CP15_SCTLR_I    0x00001000
   58: #define CP15_SCTLR_Z    0x00000800
   59: #define CP15_SCTLR_C    0x00000004
   60: #define CP15_SCTLR_A    0x00000002
   61: #define CP15_SCTLR_M    0x00000001
   62: #define CP15_SCTLR_V    0x00002000
   63: 
   64: /*
   65:  * CP15 Auxiliary Control Register(ACTLR)
   66:  */
   67: #define CP15_ACTLR_DPF          0x00000004
   68: 
   69: 
   70: /* ------------------------------------------------------------------------ */
   71: /*
   72:  * Parameter of SVC instruction 
   73:  */
   74: #define SVC_SYSCALL             6  /* micro T-Kernel system call */
   75: #define SVC_FORCE_DISPATCH      7    /* force dispatch */
   76: #define SVC_DISPATCH            8 /* task dispatcher */
   77: #define SVC_DEBUG_SUPPORT       9     /* debug support function */
   78: #define SVC_EXTENDED_SVC        10     /* Extended SVC */
   79: 
   80: /* ------------------------------------------------------------------------ */
   81: /*
   82:  * Number of SVC handlers
   83:  */
   84: #define N_SVCHDR                (11)  /* Number of SVC handlers ( used by micro T-Kernel) */
   85: 
   86: 
   87: /* ------------------------------------------------------------------------ */
   88: /*
   89:  * GIC(Generic Interrupt Controller) register
   90:  *      GIC-400 
   91:  */
   92: 
   93: /* Distributor register address */
   94: #define GICD_CTLR               (GICD_BASE + 0x0000)         /* Distributor Control Register */
   95: #define GICD_TYPER              (GICD_BASE + 0x0004)                /* Interrupt Controller Type Register */
   96: #define GICD_IIDR               (GICD_BASE + 0x0008)         /* Distributor Implementer Identification Register */
   97: 
   98: #define GICD_IGROUPR(n)         (GICD_BASE + 0x0080 + (0x04*(n)))      /* Interrupt Group Registerse */
   99: #define GICD_ISENABLER(n)       (GICD_BASE + 0x0100 + (0x04*(n)))     /* Interrupt Set-Enable Registers */
  100: #define GICD_ICENABLER(n)       (GICD_BASE + 0x0180 + (0x04*(n)))     /* Interrupt Clear-Enable Registers */
  101: #define GICD_ISPENDR(n)         (GICD_BASE + 0x0200 + (0x04*(n)))      /* Interrupt Set-Pending Registers */
  102: #define GICD_ICPENDR(n)         (GICD_BASE + 0x0280 + (0x04*(n)))      /* Interrupt Clear-Pending Registers */
  103: #define GICD_ISACTIVER(n)       (GICD_BASE + 0x0300 + (0x04*(n)))     /* Interrupt Set-Active Registers */
  104: #define GICD_ICACTIVER(n)       (GICD_BASE + 0x0380 + (0x04*(n)))     /* Interrupt Clear-Active Registers */
  105: #define GICD_IPRIORITYR(n)      (GICD_BASE + 0x0400 + (0x04*(n)))    /* Interrupt Priority Registers */
  106: #define GICD_ITARGETR(n)        (GICD_BASE + 0x0800 + (0x04*(n)))      /* Interrupt Processor Targets Registersi */
  107: #define GICD_ICFGR(n)           (GICD_BASE + 0x0C00 + (0x04*(n)))        /* Interrupt Configuration Registers */
  108: #define GICD_PPISR              (GICD_BASE + 0x0D00)                /* Private Peripheral Interrupt Status Register */
  109: #define GICD_SPISR(n)           (GICD_BASE + 0x0D04 + (0x04*(n)))        /* Shared Peripheral Interrupt Status Registers */
  110: #define GICD_SGIR               (GICD_BASE + 0x0F00)         /* Software Generated Interrupt Register */
  111: #define GICD_CPENDSGIR(n)       (GICD_BASE + 0x0F10 + (0x04*(n))) /* SGI Clear-Pending Registers */
  112: #define GICD_SPENDSGIR(n)       (GICD_BASE + 0x0F20 + (0x04*(n))) /* SGI Set-Pending Registers */
  113: 
  114: #define GICD_PIDR4              (GICD_BASE + 0x0FD0)                /* Peripheral ID 4 Register */
  115: #define GICD_PIDR5              (GICD_BASE + 0x0FD4)                /* Peripheral ID 5 Register */
  116: #define GICD_PIDR6              (GICD_BASE + 0x0FD8)                /* Peripheral ID 6 Register */
  117: #define GICD_PIDR7              (GICD_BASE + 0x0FDC)                /* Peripheral ID 7 Register */
  118: #define GICD_PIDR0              (GICD_BASE + 0x0FE0)                /* Peripheral ID 0 Register */
  119: #define GICD_PIDR1              (GICD_BASE + 0x0FE4)                /* Peripheral ID 1 Register */
  120: #define GICD_PIDR2              (GICD_BASE + 0x0FE8)                /* Peripheral ID 2 Register */
  121: #define GICD_PIDR3              (GICD_BASE + 0x0FEC)                /* Peripheral ID 3 Register */
  122: 
  123: #define GICD_CIDR0              (GICD_BASE + 0x0FF0)                /* Component ID 0 Register */
  124: #define GICD_CIDR1              (GICD_BASE + 0x0FF4)                /* Component ID 1 Register */
  125: #define GICD_CIDR2              (GICD_BASE + 0x0FF8)                /* Component ID 2 Register */
  126: #define GICD_CIDR3              (GICD_BASE + 0x0FFC)                /* Component ID 3 Register */
  127: 
  128: /* Number of registers*/
  129: #define GICD_IGROUPR_N          16
  130: #define GICD_ICFGR_N            32
  131: #define GICD_IPRIORITYR_N       128
  132: #define GICD_ITARGETR_N         128
  133: #define GICD_ISENABLER_N        16
  134: #define GICD_ICENABLER_N        16
  135: 
  136: /* CPU interface register address */
  137: #define GICC_CTLR               (GICC_BASE + 0x0000)         /* CPU Interface Control Register */
  138: #define GICC_PMR                (GICC_BASE + 0x0004)          /* Interrupt Priority Mask Register */
  139: #define GICC_BPR                (GICC_BASE + 0x0008)          /* Binary Point Register */
  140: #define GICC_IAR                (GICC_BASE + 0x000C)          /* Interrupt Acknowledge Register */
  141: #define GICC_EOIR               (GICC_BASE + 0x0010)         /* End of Interrupt Register */
  142: #define GICC_RPR                (GICC_BASE + 0x0014)          /* Running Priority Register */
  143: #define GICC_HPPIR              (GICC_BASE + 0x0018)                /* Highest Priority Pending Interrupt Register */
  144: #define GICC_ABPR               (GICC_BASE + 0x001C)         /* Aliased Binary Point Register */
  145: #define GICC_AIAR               (GICC_BASE + 0x0020)         /* Aliased Interrupt Acknowledge Register */
  146: #define GICC_AEOIR              (GICC_BASE + 0x0024)                /* Aliased End of Interrupt Register */
  147: #define GICC_AHPPIR             (GICC_BASE + 0x0028)               /* Aliased Highest Priority Pending Interrupt Register */
  148: #define GICC_APR0               (GICC_BASE + 0x00D0)         /* Active Priority Register */
  149: #define GICC_NSAPR0             (GICC_BASE + 0x00E0)               /* Non-Secure Active Priority Register */
  150: #define GICC_IIDR               (GICC_BASE + 0x00FC)         /* CPU Interface Identification Register */
  151: #define GICC_DIR                (GICC_BASE + 0x1000)          /* Deactivate Interrupt Register */
  152: 
  153: 
  154: /*
  155:  * VFP Status/Control Register (FPSCR)
  156:  */
  157: #define FPSCR_N         0x80000000     /* Cond. flag       minus */
  158: #define FPSCR_Z         0x40000000     /*          zero */
  159: #define FPSCR_C         0x20000000     /*          carry */
  160: #define FPSCR_V         0x10000000     /*          overflow */
  161: #define FPSCR_AHP       0x04000000    /* Alternative Half-Precision */
  162: #define FPSCR_DN        0x02000000     /* Default NaN */
  163: #define FPSCR_FZ        0x01000000     /* Flush to zeto */
  164: #define FPSCR_RMODE(n)  ( (n) << 22 )    /* Round mode */
  165: #define FPSCR_STRIDE(n) ( (n) << 20 )   /* Short Vector */
  166: #define FPSCR_LEN(n)    ( (n) << 16 )      /* Short Vector */
  167: #define FPSCR_IDE       0x00008000    /* Enable Trap     input denormal */
  168: #define FPSCR_IXE       0x00001000    /*         inexact */
  169: #define FPSCR_UFE       0x00000800    /*         undefflow */
  170: #define FPSCR_OFE       0x00000400    /*         overflow */
  171: #define FPSCR_DZE       0x00000200    /*         division by zero */
  172: #define FPSCR_IOE       0x00000100    /*         invalid operation */
  173: #define FPSCR_IDC       0x00000080    /* Except.Flag     input denormal */
  174: #define FPSCR_IXC       0x00000010    /*         inexact */
  175: #define FPSCR_UFC       0x00000008    /*         undeflow */
  176: #define FPSCR_OFC       0x00000004    /*         overflow */
  177: #define FPSCR_DZC       0x00000002    /*         division by zero */
  178: #define FPSCR_IOC       0x00000001    /*         invalid operation */
  179: 
  180: #define FPSCR_INIT      0x00000000   /* Init value (Full-compliance mode) */
  181: 
  182: 
  183: /* ------------------------------------------------------------------------ */
  184: /*
  185:  * memory barrier instruction
  186:  *      ISB()        Instruction Synchronization Barrier
  187:  *      DSB()        Data Synchronization Barrier
  188:  *      DMB()        Data Memory Barrier
  189:  */
  190: #define ISB()           Asm("isb")
  191: #define DSB()           Asm("dsb")
  192: #define DMB()           Asm("dmb")
  193: 
  194: /* ------------------------------------------------------------------------ */
  195: /*
  196:  * Definition of minimum system stack size
  197:  *      Minimum system stack size when setting the system stack size
  198:  *      per task by 'tk_cre_tsk().'
  199:  *  this size must be larger than the size of SStackFrame
  200:  */
  201: #if USE_FPU
  202: #define MIN_SYS_STACK_SIZE      (sizeof(SStackFrame)+sizeof(FPUContext)+128)
  203: #else
  204: #define MIN_SYS_STACK_SIZE      (sizeof(SStackFrame)+128)
  205: #endif /* USE_FPU */
  206: /*
  207:  * Default task system stack 
  208:  */
  209: 
  210: #define DEFAULT_SYS_STKSZ       (MIN_SYS_STACK_SIZE)
  211: 
  212: /* ------------------------------------------------------------------------ */
  213: /* 
  214:  *      Exception Stack Size
  215:  */
  216: #define FIQ_STACK_SIZE  (256)    /* FIQ exception stack size */
  217: #define UND_STACK_SIZE  (256)    /* Undefined instruction exception stack size */
  218: #define ABT_STACK_SIZE  (256)    /* Abort exception stack size */
  219: 
  220: /* ------------------------------------------------------------------------ */
  221: /* 
  222:  *      FPU control during interrupt handler execution
  223:  *              0: do nothing    1: Disable FPU
  224:  */
  225: #define INTHDR_DIS_FPU  1
  226: 
  227: #endif /* __SYS_SYSDEF_DEPEND_CORE_H__ */