gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.02
    4:  *
    5:  *    Copyright (C) 2006-2020 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2020/10/21 .
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      sysdef.h
   16:  *
   17:  *      System dependencies definition (RX231 CPU depended)
   18:  *      Included also from assembler program.
   19:  */
   20: 
   21: #ifndef __TK_SYSDEF_DEPEND_CPU_H__
   22: #define __TK_SYSDEF_DEPEND_CPU_H__
   23: 
   24: 
   25: /* CPU Core-dependent definition */
   26: #include "../core/rxv2/sysdef.h"
   27: 
   28: /* ------------------------------------------------------------------------ */
   29: /*
   30:  * Internal Memorie (Main RAM)  0x00000000 - 0x0000FFFF (or 0x00007FFF)
   31:  *      RX231 has two types of memory size, 32KB and 64KB.
   32:  */
   33: #define INTERNAL_RAM_SIZE       0x0000FFFF
   34: //#define INTERNAL_RAM_SIZE     0x00007FFF
   35: 
   36: #define INTERNAL_RAM_START      0x00000000
   37: #define INTERNAL_RAM_END        (INTERNAL_RAM_START+INTERNAL_RAM_SIZE)
   38: 
   39: /* ------------------------------------------------------------------------ */
   40: /*
   41:  * Initial Stack pointer (Used in initialization process)
   42:  */
   43: #define INTSTACK_TOP            INTERNAL_RAM_END+1
   44: 
   45: 
   46: /* ------------------------------------------------------------------------ */
   47: /*
   48:  * Module Stop Control 
   49:  */
   50: 
   51: /* Module Stop Control register */
   52: #define MSTPCRA         (0x00080010)
   53: #define MSTPCRB         (0x00080014)
   54: #define MSTPCRC         (0x00080018)
   55: #define MSTPCRD         (0x0008001C)
   56: 
   57: /* Module stop initial value */
   58: #if !USE_SDEV_DRV       // Do not use sample device driver
   59: 
   60: #define MSTPCRA_INI     0xEFFF7FCF  /* Enable DMAC/DTC, CMT0-1, TMR0-3 */
   61: #define MSTPCRB_INI     0xFDFFFFFF  /* Enable SCI6 */
   62: #define MSTPCRC_INI     0x7FFF0000  /* Disable Deep-Sleep mode, Enable RAM */
   63: #define MSTPCRD_INI     0xFFFFFF00
   64: 
   65: #else                   // Use the sample device driver
   66: 
   67: #define MSTPCRA_INI     0xEFFD7FCF  /* Enable DMAC/DTC, ADC, CMT0-1, TMR0-3 */
   68: #define MSTPCRB_INI     0xFDDFFFFF  /* Enable SCI6, RIIC0 */
   69: #define MSTPCRC_INI     0x7FFF0000  /* Disable Deep-Sleep mode, Enable RAM */
   70: #define MSTPCRD_INI     0xFFFFFF00
   71: 
   72: #endif /* !USE_SDEV_DRV */
   73: 
   74: 
   75: /* ------------------------------------------------------------------------ */
   76: /*
   77:  * System Clock Control 
   78:  *     Use CMT0: Compare match timer ch.0
   79:  */
   80: 
   81: /* CMT0 Registers */
   82: #define CMT_BASE        0x00088000
   83: #define CMT_STR0        (CMT_BASE + 0x0000)
   84: #define CMT0_CR         (CMT_BASE + 0x0002)
   85: #define CMT0_CNT        (CMT_BASE + 0x0004)
   86: #define CMT0_COR        (CMT_BASE + 0x0006)
   87: 
   88: #define CMT_STR0_STR0   (0x0001)
   89: #define CMT0_CR_CKS     (0x0003)
   90: #define CMT0_CR_CMIE    (0x0040)
   91: 
   92: #define MHz             (UW)(1000000UL)
   93: #define EXTAL_CLOCK     (UW)(54*MHz)
   94: 
   95: #define PCLK_DIV        (2)            /* PCLK Devistion = PCLKB of SCKCR */
   96: #define CMCR_DIV        (8)            /* PCLK/CMCR_DIV */
   97: #define CMCR_CKS_PLCK8  (0x0000) /* CMCR.CKS PCLK/8 */
   98: 
   99: #define SYSCLK_ICLK     (UW)(54*MHz)
  100: #define SYSCLK_PCLKA    (UW)(54*MHz)
  101: #define SYSCLK_PCLKB    (UW)(27*MHz)
  102: #define SYSCLK_PCLKD    (UW)(54*MHz)
  103: 
  104: /*
  105:  * Settable interval range (milli second)
  106:  */
  107: #define MIN_TIMER_PERIOD        1
  108: #define MAX_TIMER_PERIOD        50
  109: 
  110: 
  111: /*----------------------------------------------------------*/
  112: /*
  113:  * Interrupt Control
  114:  */
  115: 
  116: /*
  117:  * ICU (Interrupt Controller) register
  118:  */
  119: #define ICU_IR_BASE     0x00087000UL                /* Interrupt request reg. */
  120: #define ICU_IR(x)       (ICU_IR_BASE + (x))
  121: #define ICU_IR_IR       (0x01)
  122: 
  123: #define ICU_IER_BASE    0x00087200UL               /* Interrupt enable reg. */
  124: #define ICU_IER(x)      (ICU_IER_BASE + ((x) >> 3))
  125: #define ICU_IER_IEN(x)  (0x01 << ((x) & 7))
  126: 
  127: #define ICU_IPR_BASE    0x00087300UL               /* Interrupt priority reg. */
  128: #define ICU_IPR(x)      (ICU_IPR_BASE + (x))
  129: 
  130: #define ICU_IRQCR_BASE  0x00087500UL             /* Interrupt request control reg. */
  131: #define ICU_IRQCR(x)    (ICU_IRQCR_BASE + (x))
  132: 
  133: /*
  134:  * Number of Interrupt vectors
  135:  */
  136: #define N_INTVEC                256   /* Number of Interrupt vectors */
  137: 
  138: /*
  139:  * Interrupt Priority Levels
  140:  */
  141: #define INTPRI_MIN_INT_PRI      1    /* Lowest interrupt level */
  142: #define INTPRI_MAX_INT_PRI      15   /* Highest Interrupt level */
  143: 
  144: /*
  145:  * Interrupt used by micro T-Kernel
  146:  */
  147: #define INTNO_SYS_DISPATCH      1    /* Dispatch (reserved)*/   
  148: #define INTNO_SYS_SVC           2        /* System call (reserved) */
  149: #define INTNO_SYS_RET_INT       3     /* System call : tk_ret_int (reserved) */
  150: #define INTNO_SYS_DGSPT         4      /* Debugger support (reserved) */
  151: #define INTNO_USER_MIN          5       /* Minimum number of user-defined interrupt */
  152: 
  153: #define INTNO_SYS_TICK          28      /* Systten timer tick */
  154: 
  155: /*
  156:  * System timer interrupt level
  157:  */
  158: #define INTLEVEL_SYS_TICK       15
  159: 
  160: /*
  161:  * Time-event handler interrupt level
  162:  */
  163: #define TIMER_INTLEVEL          0
  164: 
  165: 
  166: /* ------------------------------------------------------------------------ */
  167: /*
  168:  * Pin function control
  169:  */
  170: 
  171: #define MPC_PWPR                (0x0008C11F)
  172: #define MPC_PWMR_PFSWE          (1<<6)
  173: #define MPC_PWMR_B0WI           (1<<7)
  174: 
  175: #define MPC_P0nPFS(n)           (0x0008C140+n)
  176: #define MPC_P1nPFS(n)           (0x0008C148+n)
  177: #define MPC_P2nPFS(n)           (0x0008C150+n)
  178: #define MPC_P3nPFS(n)           (0x0008C158+n)
  179: #define MPC_P4nPFS(n)           (0x0008C160+n)
  180: #define MPC_P5nPFS(n)           (0x0008C168+n)
  181: #define MPC_PAnPFS(n)           (0x0008C190+n)
  182: #define MPC_PBnPFS(n)           (0x0008C198+n)
  183: #define MPC_PCnPFS(n)           (0x0008C1A0+n)
  184: #define MPC_PDnPFS(n)           (0x0008C1A8+n)
  185: #define MPC_PEnPFS(n)           (0x0008C1B0+n)
  186: #define MPC_PHnPFS(n)           (0x0008C1C8+n)
  187: 
  188: #define MPC_PFS_ASEL            (1<<7)
  189: #define MPC_PFS_PSEL            (0x1F)
  190: 
  191: /* ------------------------------------------------------------------------ */
  192: /*
  193:  * I/O Port
  194:  */
  195: /* Port direction register */
  196: #define PORT0_PDR               (0x0008C000)
  197: #define PORT1_PDR               (0x0008C001)
  198: #define PORT2_PDR               (0x0008C002)
  199: #define PORT3_PDR               (0x0008C003)
  200: #define PORT4_PDR               (0x0008C004)
  201: #define PORT5_PDR               (0x0008C005)
  202: #define PORTA_PDR               (0x0008C00A)
  203: #define PORTB_PDR               (0x0008C00B)
  204: #define PORTC_PDR               (0x0008C00C)
  205: #define PORTD_PDR               (0x0008C00D)
  206: #define PORTE_PDR               (0x0008C00E)
  207: #define PORTH_PDR               (0x0008C011)
  208: #define PORTJ_PDR               (0x0008C012)
  209: 
  210: /* Port output data register */
  211: #define PORT0_PODR              (0x0008C020)
  212: #define PORT1_PODR              (0x0008C021)
  213: #define PORT2_PODR              (0x0008C022)
  214: #define PORT3_PODR              (0x0008C023)
  215: #define PORT4_PODR              (0x0008C024)
  216: #define PORT5_PODR              (0x0008C025)
  217: #define PORTA_PODR              (0x0008C02A)
  218: #define PORTB_PODR              (0x0008C02B)
  219: #define PORTC_PODR              (0x0008C02C)
  220: #define PORTD_PODR              (0x0008C02D)
  221: #define PORTE_PODR              (0x0008C02E)
  222: #define PORTH_PODR              (0x0008C031)
  223: #define PORTJ_PODR              (0x0008C032)
  224: 
  225: /* Port input data register */
  226: #define PORT0_PIDR              (0x0008C040)
  227: #define PORT1_PIDR              (0x0008C041)
  228: #define PORT2_PIDR              (0x0008C042)
  229: #define PORT3_PIDR              (0x0008C043)
  230: #define PORT4_PIDR              (0x0008C044)
  231: #define PORT5_PIDR              (0x0008C045)
  232: #define PORTA_PIDR              (0x0008C04A)
  233: #define PORTB_PIDR              (0x0008C04B)
  234: #define PORTC_PIDR              (0x0008C04C)
  235: #define PORTD_PIDR              (0x0008C04D)
  236: #define PORTE_PIDR              (0x0008C04E)
  237: #define PORTH_PIDR              (0x0008C051)
  238: #define PORTJ_PIDR              (0x0008C052)
  239: 
  240: /* Port mode register */
  241: #define PORT0_PMR               (0x0008C060)
  242: #define PORT1_PMR               (0x0008C061)
  243: #define PORT2_PMR               (0x0008C062)
  244: #define PORT3_PMR               (0x0008C063)
  245: #define PORT4_PMR               (0x0008C064)
  246: #define PORT5_PMR               (0x0008C065)
  247: #define PORTA_PMR               (0x0008C06A)
  248: #define PORTB_PMR               (0x0008C06B)
  249: #define PORTC_PMR               (0x0008C06C)
  250: #define PORTD_PMR               (0x0008C06D)
  251: #define PORTE_PMR               (0x0008C06E)
  252: #define PORTH_PMR               (0x0008C071)
  253: #define PORTJ_PMR               (0x0008C072)
  254: 
  255: /* Open drain control register 0 */
  256: #define PORT1_ODR0              (0x0008C082)
  257: #define PORT2_ODR0              (0x0008C084)
  258: #define PORT3_ODR0              (0x0008C086)
  259: #define PORT5_ODR0              (0x0008C08A)
  260: #define PORTA_ODR0              (0x0008C094)
  261: #define PORTB_ODR0              (0x0008C096)
  262: #define PORTC_ODR0              (0x0008C098)
  263: #define PORTE_ODR0              (0x0008C09C)
  264: #define PORTJ_ODR0              (0x0008C0A4)
  265: 
  266: /* Open drain control register 1 */
  267: #define PORT1_ODR1              (0x0008C083)
  268: #define PORT2_ODR1              (0x0008C085)
  269: #define PORT3_ODR1              (0x0008C087)
  270: #define PORT5_ODR1              (0x0008C08B)
  271: #define PORTA_ODR1              (0x0008C095)
  272: #define PORTB_ODR1              (0x0008C097)
  273: #define PORTC_ODR1              (0x0008C099)
  274: #define PORTE_ODR1              (0x0008C09D)
  275: 
  276: /* Pull-up control register */
  277: #define PORT0_PCR               (0x0008C0C0)
  278: #define PORT1_PCR               (0x0008C0C1)
  279: #define PORT2_PCR               (0x0008C0C2)
  280: #define PORT3_PCR               (0x0008C0C3)
  281: #define PORT4_PCR               (0x0008C0C4)
  282: #define PORT5_PCR               (0x0008C0C5)
  283: #define PORTA_PCR               (0x0008C0CA)
  284: #define PORTB_PCR               (0x0008C0CB)
  285: #define PORTC_PCR               (0x0008C0CC)
  286: #define PORTD_PCR               (0x0008C0CD)
  287: #define PORTE_PCR               (0x0008C0CE)
  288: #define PORTH_PCR               (0x0008C0D1)
  289: #define PORTJ_PCR               (0x0008C0D2)
  290: 
  291: /* Port switching register */
  292: #define PORT_PSRA               (0x0008C121)
  293: #define PORT_PSRB               (0x0008C120)
  294: 
  295: /* Drive capacity control register */
  296: #define PORT1_DSCR              (0x0008C0E1)
  297: #define PORT2_DSCR              (0x0008C0E2)
  298: #define PORT3_DSCR              (0x0008C0E3)
  299: #define PORT5_DSCR              (0x0008C0E5)
  300: #define PORTA_DSCR              (0x0008C0EA)
  301: #define PORTB_DSCR              (0x0008C0EB)
  302: #define PORTC_DSCR              (0x0008C0EC)
  303: #define PORTD_DSCR              (0x0008C0ED)
  304: #define PORTE_DSCR              (0x0008C0EE)
  305: #define PORTH_DSCR              (0x0008C0F1)
  306: #define PORTJ_DSCR              (0x0008C0F2)
  307: 
  308: 
  309: /* ------------------------------------------------------------------------ */
  310: /*
  311:  * Physical timer
  312:  */
  313: #define CPU_HAS_PTMR    (1)
  314: 
  315: /* TMR Register definition */
  316: #define TMR01_BASE              0x00088200
  317: #define TMR23_BASE              0x00088210
  318: 
  319: #define TCR                     0x0000
  320: #define TCSR                    0x0002
  321: #define TCORA                   0x0004
  322: #define TCORB                   0x0006
  323: #define TCNT                    0x0008
  324: #define TCCR                    0x000A
  325: #define TCSTR                   0x000C
  326: 
  327: #define TCR_CCLR_CMA            (1<<3)            // Cleared by compare match A
  328: #define TCR_OVIE                (1<<5)                // Enable OVIn
  329: #define TCR_CMIEA               (1<<6)               // Enable CMIAn
  330: #define TCR_CMIEB               (1<<7)               // Enable CMIBn
  331: 
  332: #define TCCR_CSS_16BIT          (0x18)
  333: 
  334: /* Physical timer clock */
  335: #define TMR01_CLOCK             (0x08)             // Count PCLK
  336: #define TMR23_CLOCK             (0x08)             // Count PCLK
  337: 
  338: /* Physical timer interrupt number */
  339: #define INTNO_CMIA0             174
  340: #define INTNO_CMIB0             175
  341: #define INTNO_OVI0              176
  342: #define INTNO_CMIA1             177
  343: #define INTNO_CMIB1             178
  344: #define INTNO_OVI1              179
  345: #define INTNO_CMIA2             180
  346: #define INTNO_CMIB2             181
  347: #define INTNO_OVI2              182
  348: #define INTNO_CMIA3             183
  349: #define INTNO_CMIB3             184
  350: #define INTNO_OVI3              185
  351: 
  352: /* Physical timer interrupt priority */
  353: #define INTPRI_TMR01            5
  354: #define INTPRI_TMR23            5
  355: 
  356: /* Phycail timer Maximum count */
  357: #define PTMR_MAX_CNT    (0x0000FFFF)
  358: 
  359: 
  360: /* ------------------------------------------------------------------------ */
  361: /*
  362:  * Coprocessor
  363:  */
  364: #define CPU_HAS_FPU                     1
  365: #define CPU_HAS_DPS                     1
  366: 
  367: /*
  368:  *  Number of coprocessors to use. Depends on user configuration
  369:  */
  370: #if USE_FPU && USE_DSP
  371: #define NUM_COPROCESSOR         2
  372: #elif USE_FPU
  373: #define NUM_COPROCESSOR         1
  374: #elif USE_DSP
  375: #define NUM_COPROCESSOR         1
  376: #else
  377: #define NUM_COPROCESSOR         0
  378: #endif
  379: 
  380: 
  381: #endif /* __TK_SYSDEF_DEPEND_CPU_H__ */