gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      sysdef.h
   16:  *
   17:  *      System dependencies definition (RZ/A2M depended)
   18:  *      Included also from assembler program.
   19:  */
   20: 
   21: #ifndef __TK_SYSDEF_DEPEND_CPU_H__
   22: #define __TK_SYSDEF_DEPEND_CPU_H__
   23: 
   24: 
   25: /* CPU Core-dependent definition */
   26: #include "../core/armv7a/sysdef.h"
   27: 
   28: /* ------------------------------------------------------------------------ */
   29: /*
   30:  * RAM Map (Internal Memorie 0x80020000 - 0x803FFFFF)
   31:  *       Backup RAM     0x80000000 - 0x8001FFFF
   32:  *       Cached RAM     0x80020000 - 0x802FFFFF
   33:  *       Uncached RAM   0x80300000 - 0x803FBFFF
   34:  *       TTB RAM        0x803FC000 - 0c803FFFFF
   35:  */
   36: 
   37: #define IRAM_START_ADDR                 0x80000000
   38: #define IRAM_SIZE                       0x00400000
   39: #define IRAM_UNCACHED_SIZE              0x00200000
   40: 
   41: #define IRAM_CACHED_START_ADDR          IRAM_START_ADDR
   42: #define IRAM_CACHED_SIZE                (IRAM_SIZE - IRAM_UNCACHED_SIZE)
   43: #define IRAM_CACHED_END_ADDR            (IRAM_CACHED_START_ADDR + IRAM_CACHED_SIZE)
   44: #define IRAM_UNCACHED_START_ADDR        IRAM_CACHED_END_ADDR
   45: 
   46: /*
   47:  * mT-Kernel RAM area (OS uses cached RAM area.)
   48: */
   49: #define INTERNAL_RAM_SIZE       0x002E0000
   50: #define INTERNAL_RAM_START      0x80020000
   51: #define INTERNAL_RAM_END        (INTERNAL_RAM_START+INTERNAL_RAM_SIZE)
   52: 
   53: /* ------------------------------------------------------------------------ */
   54: /*
   55:  * Initial Stack pointer (Used in initialization process)
   56:  */
   57: #define INITIAL_SP              INTERNAL_RAM_END
   58: 
   59: /* ------------------------------------------------------------------------ */
   60: /*
   61:  * TTB(translation table base) Attribute
   62:  */
   63: #define TTB_ATR_STRGLY                          0x00DF2       /* 0000_0000_0000_0000_0000_1101_1111_0010    Secure Strongly-ordered memory */
   64: #define TTB_ATR_STRGLY_NS                       0x80DF2     /* 0000_0000_0000_1000_0000_1101_1111_0010    Non-secure Strongly-ordered memory */
   65: #define TTB_ATR_DEVICE                          0x00DF6       /* 0000_0000_0000_0000_0000_1101_1111_0110    Secure Device memory */
   66: #define TTB_ATR_DEVICE_NS                       0x80DF6     /* 0000_0000_0000_1000_0000_1101_1111_0110    Non-secure Device memory */
   67: #define TTB_ATR_NORMAL_NOT_CACHE                0x04DE2       /* 0000_0000_0000_0000_0100_1101_1110_0010    Outer and inner Non-cacheable, and Secure Normal memory */
   68: #define TTB_ATR_NORMAL_NOT_CACHE_NS             0x84DE2    /* 0000_0000_0000_1000_0100_1101_1110_0010    Outer and inner Non-cacheable, and Non-secure Normal memory */
   69: #define TTB_ATR_NORMAL_CACHE                    0x01DEE  /* 0000_0000_0000_0000_0001_1101_1110_1110    Outer and inner Write-Back Write-Allocate Cacheable, and Secure Normal memory */
   70: #define TTB_ATR_NORMAL_CACHE_NS                 0x81DEE       /* 0000_0000_0000_1000_0001_1101_1110_1110    Outer and inner Write-Back Write-Allocate Cacheable, and Non-secure Normal memory */
   71: #define TTB_ATR_NORMAL_L1_CACHE_L2_NOT_CACHE    0x04DE6    /* 0000_0000_0000_0000_0100_1101_1110_0110    Outer Non-cacheable, Inner Write-Back Write-Allocate Cacheable, and Secure Normal memory */
   72: #define TTB_ATR_NORMAL_L1_CACHE_L2_NOT_CACHE_NS 0x84DE6 /* 0000_0000_0000_1000_0100_1101_1110_0110    Outer Non-cacheable, Inner Write-Back Write-Allocate Cacheable, and Non-secure Normal memory */
   73: 
   74: 
   75: /* ------------------------------------------------------------------------ */
   76: /*
   77:  * Power & Clock Control
   78:  */
   79: 
   80: /*
   81:  * CPG registers
   82: */
   83: #define CPG_FRQCR               0xFCFE0010
   84: 
   85: /* CPG initial value */
   86: /*      PLL(x88), I:G:B:P1:P0 = 22:11:5.5:2.75:1.375 
   87:  *      CKIO:Output at time usually,
   88:  *      Output when bus right is opened,
   89:  *      output at standby"L"
   90:  */
   91: #define CPG_FRQCR_INIVAL        0x1012
   92: #define CLOCK_in        24     /* Clockin  = 24MH */
   93: #define CLOCK_I         528    /* I  Clock = 528MHz */
   94: #define CLOCK_G         264    /* G  Clock = 264MHz */
   95: #define CLOCK_B         132    /* B  Clock = 132MHz */
   96: #define CLOCK_P1        66     /* P1 Clock = 66MHz */
   97: #define CLOCK_P0        33     /* P0 Clock = 33MHz */
   98: 
   99: #define CPG_CKIOSEL             0xFCFE0100
  100: #define CPG_SCLKSEL             0xFCFE0104
  101: 
  102: /*
  103:  * Low power consumption mode registers
  104: */
  105: #define CPG_SYSCR1              0xFCFE0400
  106: #define CPG_SYSCR2              0xFCFE0404
  107: #define CPG_SYSCR3              0xFCFE0408
  108: 
  109: /*
  110:  * Stanby control registers
  111:  */
  112: #define CPG_STBCR1              0xFCFE0020
  113: #define CPG_STBCR2              0xFCFE0024
  114: #define CPG_STBCR3              0xFCFE0420
  115: #define CPG_STBCR4              0xFCFE0424
  116: #define CPG_STBCR5              0xFCFE0428
  117: #define CPG_STBCR6              0xFCFE042C
  118: #define CPG_STBCR7              0xFCFE0430
  119: #define CPG_STBCR8              0xFCFE0434
  120: #define CPG_STBCR9              0xFCFE0438
  121: #define CPG_STBCR10             0xFCFE043C
  122: #define CPG_STBCR11             0xFCFE0440
  123: 
  124: 
  125: /* ------------------------------------------------------------------------ */
  126: /*
  127:  * Level2 cache controller (PL310) registers
  128:  */
  129: #define PL310_BASE              0x1F003000
  130: #define PL310_POWER_CTL         (PL310_BASE + 0x0F80)          /* Power Control Register */
  131: 
  132: /* ------------------------------------------------------------------------ */
  133: /*
  134:  * System Timer Clock
  135:  */
  136: 
  137: /* OSTM0 : OS timer ch.0 */
  138: #define OSTM0_BASE      0xE803B000
  139: #define OSTM0_CMP       (OSTM0_BASE + 0x0000)
  140: #define OSTM0_CNT       (OSTM0_BASE + 0x0004)
  141: #define OSTM0_TE        (OSTM0_BASE + 0x0010)
  142: #define OSTM0_TS        (OSTM0_BASE + 0x0014)
  143: #define OSTM0_TT        (OSTM0_BASE + 0x0018)
  144: #define OSTM0_CTL       (OSTM0_BASE + 0x0020)
  145: 
  146: 
  147: /* P1 clock 66.666MHz */
  148: #define TMCLK                   66              /* Timer clock input (MHz) */
  149: #define TMCLK_KHz               66666                /* Timer clock input (KHz) */
  150: #define COUNT_PER_SEC           66666666LL       /* count/sec */
  151: #define NSEC_PER_COUNT          15              /* nsec/count */
  152: 
  153: 
  154: /* Settable interval range (millisecond) */
  155: #define MIN_TIMER_PERIOD        1
  156: #define MAX_TIMER_PERIOD        50
  157: 
  158: /* ------------------------------------------------------------------------ */
  159: /*
  160:  * GIC(Generic Interrupt Controller) -400
  161:  */
  162: #define GICD_BASE       0xE8221000UL          /* Distributor register base address */
  163: #define GICC_BASE       0xE8222000UL          /* CPU interface register base address */
  164: 
  165: 
  166: /* ------------------------------------------------------------------------ */
  167: /*
  168:  * Number of Interrupt vectors
  169:  */
  170: #define N_INTVEC                (512)         /* Number of Interrupt vectors */
  171: 
  172: /*
  173:  * The number of the implemented bit width for priority value fields.
  174:  */
  175: #define INTPRI_BITWIDTH         5      /* bitwidth of interrupt priority */
  176: 
  177: /*
  178:  * Interrupt Priority Levels
  179:  */
  180: #define INTPRI_SHIFT            (8 - INTPRI_BITWIDTH)
  181: #define INTPRI_HIGHEST          0       /* Highest interrupt level */
  182: #define INTPRI_LOWEST           31       /* Lowest  interrupt level  */
  183: #define INTPRI_SYSTICK          1       /* interrupt priority for SysTick */
  184: 
  185: /*
  186:  * Interrupt used by micro T-Kernel
  187:  */
  188: #define INTNO_SW0               0    /* GIC software interrupt 0 (min.) */
  189: #define INTNO_SW15              15  /* GIC software interrupt 15 (max.) */
  190: 
  191: #define INTNO_SYSTICK           88       /* System Timer interrupt (OSTIM0) */
  192: 
  193: /*
  194:  * Time-event handler interrupt level
  195:  */
  196: #define TIMER_INTLEVEL          0
  197: 
  198: 
  199: /* ------------------------------------------------------------------------ */
  200: /*
  201:  * General purpose I / O port
  202:  */
  203: #define PORT_BASE       0xFCFFE000
  204: 
  205: /* Port direction register */
  206: #define PORT0_PDR       (PORT_BASE + 0x0000)
  207: #define PORT1_PDR       (PORT_BASE + 0x0002)
  208: #define PORT2_PDR       (PORT_BASE + 0x0004)
  209: #define PORT3_PDR       (PORT_BASE + 0x0006)
  210: #define PORT4_PDR       (PORT_BASE + 0x0008)
  211: #define PORT5_PDR       (PORT_BASE + 0x000A)
  212: #define PORT6_PDR       (PORT_BASE + 0x000C)
  213: #define PORT7_PDR       (PORT_BASE + 0x000E)
  214: #define PORT8_PDR       (PORT_BASE + 0x0010)
  215: #define PORT9_PDR       (PORT_BASE + 0x0012)
  216: #define PORTA_PDR       (PORT_BASE + 0x0014)
  217: #define PORTB_PDR       (PORT_BASE + 0x0016)
  218: #define PORTC_PDR       (PORT_BASE + 0x0018)
  219: #define PORTD_PDR       (PORT_BASE + 0x001A)
  220: #define PORTE_PDR       (PORT_BASE + 0x001C)
  221: #define PORTF_PDR       (PORT_BASE + 0x001E)
  222: #define PORTG_PDR       (PORT_BASE + 0x0020)
  223: #define PORTH_PDR       (PORT_BASE + 0x0022)
  224: #define PORTJ_PDR       (PORT_BASE + 0x0024)
  225: #define PORTK_PDR       (PORT_BASE + 0x0026)
  226: #define PORTL_PDR       (PORT_BASE + 0x0028)
  227: #define PORTM_PDR       (PORT_BASE + 0x002A)
  228: 
  229: /* Port output data register */
  230: #define PORT0_PODR      (PORT_BASE + 0x0040)
  231: #define PORT1_PODR      (PORT_BASE + 0x0041)
  232: #define PORT2_PODR      (PORT_BASE + 0x0042)
  233: #define PORT3_PODR      (PORT_BASE + 0x0043)
  234: #define PORT4_PODR      (PORT_BASE + 0x0044)
  235: #define PORT5_PODR      (PORT_BASE + 0x0045)
  236: #define PORT6_PODR      (PORT_BASE + 0x0046)
  237: #define PORT7_PODR      (PORT_BASE + 0x0047)
  238: #define PORT8_PODR      (PORT_BASE + 0x0048)
  239: #define PORT9_PODR      (PORT_BASE + 0x0049)
  240: #define PORTA_PODR      (PORT_BASE + 0x004A)
  241: #define PORTB_PODR      (PORT_BASE + 0x004B)
  242: #define PORTC_PODR      (PORT_BASE + 0x004C)
  243: #define PORTD_PODR      (PORT_BASE + 0x004D)
  244: #define PORTE_PODR      (PORT_BASE + 0x004E)
  245: #define PORTF_PODR      (PORT_BASE + 0x004F)
  246: #define PORTG_PODR      (PORT_BASE + 0x0050)
  247: #define PORTH_PODR      (PORT_BASE + 0x0051)
  248: #define PORTJ_PODR      (PORT_BASE + 0x0052)
  249: #define PORTK_PODR      (PORT_BASE + 0x0053)
  250: #define PORTL_PODR      (PORT_BASE + 0x0054)
  251: #define PORTM_PODR      (PORT_BASE + 0x0055)
  252: 
  253: /* Port input data register */
  254: #define PORT0_PIDR      (PORT_BASE + 0x0060)
  255: #define PORT1_PIDR      (PORT_BASE + 0x0061)
  256: #define PORT2_PIDR      (PORT_BASE + 0x0062)
  257: #define PORT3_PIDR      (PORT_BASE + 0x0063)
  258: #define PORT4_PIDR      (PORT_BASE + 0x0064)
  259: #define PORT5_PIDR      (PORT_BASE + 0x0065)
  260: #define PORT6_PIDR      (PORT_BASE + 0x0066)
  261: #define PORT7_PIDR      (PORT_BASE + 0x0067)
  262: #define PORT8_PIDR      (PORT_BASE + 0x0068)
  263: #define PORT9_PIDR      (PORT_BASE + 0x0069)
  264: #define PORTA_PIDR      (PORT_BASE + 0x006A)
  265: #define PORTB_PIDR      (PORT_BASE + 0x006B)
  266: #define PORTC_PIDR      (PORT_BASE + 0x006C)
  267: #define PORTD_PIDR      (PORT_BASE + 0x006D)
  268: #define PORTE_PIDR      (PORT_BASE + 0x006E)
  269: #define PORTF_PIDR      (PORT_BASE + 0x006F)
  270: #define PORTG_PIDR      (PORT_BASE + 0x0070)
  271: #define PORTH_PIDR      (PORT_BASE + 0x0071)
  272: #define PORTJ_PIDR      (PORT_BASE + 0x0072)
  273: #define PORTK_PIDR      (PORT_BASE + 0x0073)
  274: #define PORTL_PIDR      (PORT_BASE + 0x0074)
  275: #define PORTM_PIDR      (PORT_BASE + 0x0075)
  276: 
  277: /* Port mode register */
  278: #define PORT0_PMR       (PORT_BASE + 0x0080)
  279: #define PORT1_PMR       (PORT_BASE + 0x0081)
  280: #define PORT2_PMR       (PORT_BASE + 0x0082)
  281: #define PORT3_PMR       (PORT_BASE + 0x0083)
  282: #define PORT4_PMR       (PORT_BASE + 0x0084)
  283: #define PORT5_PMR       (PORT_BASE + 0x0085)
  284: #define PORT6_PMR       (PORT_BASE + 0x0086)
  285: #define PORT7_PMR       (PORT_BASE + 0x0087)
  286: #define PORT8_PMR       (PORT_BASE + 0x0088)
  287: #define PORT9_PMR       (PORT_BASE + 0x0089)
  288: #define PORTA_PMR       (PORT_BASE + 0x008A)
  289: #define PORTB_PMR       (PORT_BASE + 0x008B)
  290: #define PORTC_PMR       (PORT_BASE + 0x008C)
  291: #define PORTD_PMR       (PORT_BASE + 0x008D)
  292: #define PORTE_PMR       (PORT_BASE + 0x008E)
  293: #define PORTF_PMR       (PORT_BASE + 0x008F)
  294: #define PORTG_PMR       (PORT_BASE + 0x0090)
  295: #define PORTH_PMR       (PORT_BASE + 0x0091)
  296: #define PORTJ_PMR       (PORT_BASE + 0x0092)
  297: #define PORTK_PMR       (PORT_BASE + 0x0093)
  298: #define PORTL_PMR       (PORT_BASE + 0x0094)
  299: #define PORTM_PMR       (PORT_BASE + 0x0095)
  300: 
  301: /* Drive capacity control register */
  302: #define PORT0_DSCR      (PORT_BASE + 0x0140)
  303: #define PORT1_DSCR      (PORT_BASE + 0x0142)
  304: #define PORT2_DSCR      (PORT_BASE + 0x0144)
  305: #define PORT3_DSCR      (PORT_BASE + 0x0146)
  306: #define PORT4_DSCR      (PORT_BASE + 0x0148)
  307: #define PORT5_DSCR      (PORT_BASE + 0x014A)
  308: #define PORT6_DSCR      (PORT_BASE + 0x014C)
  309: #define PORT7_DSCR      (PORT_BASE + 0x014E)
  310: #define PORT8_DSCR      (PORT_BASE + 0x0150)
  311: #define PORT9_DSCR      (PORT_BASE + 0x0152)
  312: #define PORTA_DSCR      (PORT_BASE + 0x0154)
  313: #define PORTB_DSCR      (PORT_BASE + 0x0156)
  314: #define PORTC_DSCR      (PORT_BASE + 0x0158)
  315: #define PORTD_DSCR      (PORT_BASE + 0x015A)
  316: #define PORTE_DSCR      (PORT_BASE + 0x015C)
  317: #define PORTF_DSCR      (PORT_BASE + 0x015E)
  318: #define PORTG_DSCR      (PORT_BASE + 0x0160)
  319: #define PORTH_DSCR      (PORT_BASE + 0x0162)
  320: #define PORTJ_DSCR      (PORT_BASE + 0x0164)
  321: #define PORTK_DSCR      (PORT_BASE + 0x0166)
  322: #define PORTL_DSCR      (PORT_BASE + 0x0168)
  323: #define PORTM_DSCR      (PORT_BASE + 0x016A)
  324: 
  325: /* Pin function selection register */
  326: #define PORT0n_PFS(n)   (PORT_BASE + 0x0200 + (n))
  327: #define PORT1n_PFS(n)   (PORT_BASE + 0x0208 + (n))
  328: #define PORT2n_PFS(n)   (PORT_BASE + 0x0210 + (n))
  329: #define PORT3n_PFS(n)   (PORT_BASE + 0x0218 + (n))
  330: #define PORT4n_PFS(n)   (PORT_BASE + 0x0220 + (n))
  331: #define PORT5n_PFS(n)   (PORT_BASE + 0x0228 + (n))
  332: #define PORT6n_PFS(n)   (PORT_BASE + 0x0230 + (n))
  333: #define PORT7n_PFS(n)   (PORT_BASE + 0x0238 + (n))
  334: #define PORT8n_PFS(n)   (PORT_BASE + 0x0240 + (n))
  335: #define PORT9n_PFS(n)   (PORT_BASE + 0x0248 + (n))
  336: #define PORTAn_PFS(n)   (PORT_BASE + 0x0250 + (n))
  337: #define PORTBn_PFS(n)   (PORT_BASE + 0x0258 + (n))
  338: #define PORTCn_PFS(n)   (PORT_BASE + 0x0260 + (n))
  339: #define PORTDn_PFS(n)   (PORT_BASE + 0x0268 + (n))
  340: #define PORTEn_PFS(n)   (PORT_BASE + 0x0270 + (n))
  341: #define PORTFn_PFS(n)   (PORT_BASE + 0x0278 + (n))
  342: #define PORTGn_PFS(n)   (PORT_BASE + 0x0280 + (n))
  343: #define PORTHn_PFS(n)   (PORT_BASE + 0x0288 + (n))
  344: #define PORTJn_PFS(n)   (PORT_BASE + 0x0290 + (n))
  345: #define PORTKn_PFS(n)   (PORT_BASE + 0x0298 + (n))
  346: #define PORTLn_PFS(n)   (PORT_BASE + 0x02A0 + (n))
  347: #define PORTMn_PFS(n)   (PORT_BASE + 0x02A8 + (n))
  348: 
  349: #define PORT_PFS_ISEL           (0x40)
  350: #define PORT_PFS_PSEL(n)        (0x07 & n)
  351: 
  352: #define PORT_PWPR       (PORT_BASE + 0x02FF)          /* Write protect register */
  353: #define PORT_PWPR_B0WI  0b10000000                       /* PFSWE write permission bit */
  354: #define PORT_PWPR_PFSWE 0b01000000                      /* PFS write permission bit */
  355: 
  356: /* ------------------------------------------------------------------------ */
  357: /*
  358:  * Physical timer (for RZ/A2M)
  359:  */
  360: #define CPU_HAS_PTMR    (1)
  361: 
  362: /* Timer register definition */
  363: #define OSTM1_BASE      0xE803C000
  364: #define OSTM2_BASE      0xE803D000
  365: 
  366: #define OSTMnCMP        0x00
  367: #define OSTMnCNT        0x04
  368: #define OSTMnTE         0x10
  369: #define OSTMnTS         0x14
  370: #define OSTMnTT         0x18
  371: #define OSTMnCTL        0x20
  372: 
  373: #define OSTMnCTL_MD1    0x02
  374: #define OSTMnCTL_MD0    0x01
  375: 
  376: /* Physical timer interrupt number */
  377: #define INTNO_OSTM1     89
  378: #define INTNO_OSTM2     90
  379: 
  380: /* Physical timer interrupt priority */
  381: #define INTPRI_OSTM1    5
  382: #define INTPRI_OSTM2    5
  383: 
  384: /* OS Timer clock 33.333MHz */
  385: #define PTMCLK          33
  386: 
  387: /* Phycail timer Maximum count */
  388: #define PTMR_MAX_CNT    (0xFFFFFFFF)
  389: 
  390: 
  391: /* ------------------------------------------------------------------------ */
  392: /*
  393:  * Coprocessor
  394:  */
  395: #define CPU_HAS_FPU                     1
  396: #define CPU_HAS_DPS                     0
  397: 
  398: /*
  399:  *  Number of coprocessors to use. 
  400:  *    There is no coprocessor for this microcomputer.
  401:  */
  402: #if USE_FPU
  403: #define NUM_COPROCESSOR         1
  404: #else
  405: #define NUM_COPROCESSOR         0
  406: #endif
  407: 
  408: #endif /* __TK_SYSDEF_DEPEND_CPU_H__ */