gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      sysdef.h
   16:  *
   17:  *      System dependencies definition (STM32L4 depended)
   18:  *      Included also from assembler program.
   19:  */
   20: 
   21: #ifndef __TK_SYSDEF_DEPEND_CPU_H__
   22: #define __TK_SYSDEF_DEPEND_CPU_H__
   23: 
   24: #include "../../../machine.h"
   25: 
   26: /* CPU Core-dependent definition */
   27: #include "../core/armv7m/sysdef.h"
   28: 
   29: /* ------------------------------------------------------------------------ */
   30: /*
   31:  * Internal Memorie (Main RAM)
   32:  */
   33: 
   34: /* STM32L478, STM32L486 Internal SRAM1   0x20000000 - 0x20017FFF  (Size 96KB) */
   35: #if CPU_STM32L476 | CPU_STM32L486
   36: #define INTERNAL_RAM_SIZE       0x00018000
   37: #define INTERNAL_RAM_START      0x20000000
   38: #endif
   39: 
   40: #define INTERNAL_RAM_END        (INTERNAL_RAM_START+INTERNAL_RAM_SIZE)
   41: 
   42: /* ------------------------------------------------------------------------ */
   43: /*
   44:  * Initial Stack pointer (Used in initialization process)
   45:  */
   46: #define INITIAL_SP              INTERNAL_RAM_END
   47: 
   48: 
   49: /* ------------------------------------------------------------------------ */
   50: /*
   51:  * System configuration controler (SYSCFG)
   52:  */
   53: 
   54: #define SYSCFG_BASE     0x40010000
   55: 
   56: #define SYSCFG_MEMRMP   (SYSCFG_BASE+0x0000)
   57: #define SYSCFG_CFGR1    (SYSCFG_BASE+0x0004)
   58: #define SYSCFG_EXTICR1  (SYSCFG_BASE+0x0008)
   59: #define SYSCFG_EXTICR2  (SYSCFG_BASE+0x000C)
   60: #define SYSCFG_EXTICR3  (SYSCFG_BASE+0x0010)
   61: #define SYSCFG_EXTICR4  (SYSCFG_BASE+0x0014)
   62: #define SYSCFG_SCSR     (SYSCFG_BASE+0x0018)
   63: #define SYSCFG_CFGR2    (SYSCFG_BASE+0x001C)
   64: #define SYSCFG_SWPR     (SYSCFG_BASE+0x0020)
   65: #define SYSCFG_SKR      (SYSCFG_BASE+0x0024)
   66: #define SYSCFG_SWPR2    (SYSCFG_BASE+0x0028)
   67: 
   68: 
   69: /* ------------------------------------------------------------------------ */
   70: /*
   71:  * Internal flash memory controls
   72:  */
   73: 
   74: #define FLASH_BASE      0x40022000
   75: 
   76: #define FLASH_ACR       (FLASH_BASE+0x0000)   /* Flash access control register */
   77: #define FLASH_PDKEYR    (FLASH_BASE+0x0004)        /* Flash Power-down key register */
   78: #define FLASH_KEYR      (FLASH_BASE+0x0008)  /* Flash key register */
   79: #define FLASH_OPTKEYR   (FLASH_BASE+0x000C)       /* Flash option key register */
   80: #define FLASH_SR        (FLASH_BASE+0x0010)    /* Flash status register */
   81: #define FLASH_CR        (FLASH_BASE+0x0014)    /* Flash control register */
   82: #define FLASH_ECCR      (FLASH_BASE+0x0018)  /* Flash ECC register */
   83: #define FLASH_OPTR      (FLASH_BASE+0x0020)  /* Flash option register */
   84: #define FLASH_PCROP1SR  (FLASH_BASE+0x0024)      /* Flash PCROP1 Start address register */
   85: #define FLASH_PCROP1ER  (FLASH_BASE+0x0028)      /* Flash PCROP1 End address register */
   86: #define FLASH_WRP1AR    (FLASH_BASE+0x002C)        /* Flash WRP1 area A address register */
   87: #define FLASH_WRP1BR    (FLASH_BASE+0x0030)        /* Flash WRP1 area B address register */
   88: #define FLASH_PCROP2SR  (FLASH_BASE+0x0044)      /* Flash PCROP2 Start address register */
   89: #define FLASH_PCROP2ER  (FLASH_BASE+0x0048)      /* Flash PCROP2 End address register */
   90: #define FLASH_WRP2AR    (FLASH_BASE+0x004C)        /* Flash WRP2 area A address register */
   91: #define FLASH_WRP2BR    (FLASH_BASE+0x0050)        /* Flash WRP2 area B address register */
   92: #define FLASH_CFGR      (FLASH_BASE+0x0130)  /* Flash configuration register */
   93: 
   94: 
   95: /* FLASH_ACR bit definition */
   96: #define FLASH_ACR_SLEEP_PD      0x00004000   // Flash Power-down mode during Sleep or Low-power sleep mode
   97: #define FLASH_ACR_RUN_PD        0x00002000     // Flash Power-down mode during Run or Low-power run mode
   98: #define FLASH_ACR_DCRST         0x00001000     // Data cache reset
   99: #define FLASH_ACR_ICRST         0x00000800     // Instruction cache reset
  100: #define FLASH_ACR_DCEN          0x00000400      // Data cache enable
  101: #define FLASH_ACR_ICEN          0x00000200      // Instruction cache enable
  102: #define FLASH_ACR_PRFTEN        0x00000100     // Prefetch enable
  103: #define FLASH_ACR_LATENCY_MASK  0x00000007       // Latency
  104: #define FLASH_ACR_LATENCY(n)    (((_UW)(n)<<0) & FLASH_ACR_LATENCY_MASK)
  105: 
  106: /* ------------------------------------------------------------------------ */
  107: /*
  108:  * Power & Clock Control
  109:  */
  110: /*
  111:  * PWR (Power Control) registers
  112: */
  113: #define PWR_BASE        0x40007000
  114: #define PWR_CR1         (PWR_BASE+0x0000)      /* Power control register 1 */
  115: #define PWR_CR2         (PWR_BASE+0x0004)      /* Power control register 2 */
  116: #define PWR_CR3         (PWR_BASE+0x0008)      /* Power control register 3 */
  117: #define PWR_CR4         (PWR_BASE+0x000C)      /* Power control register 4 */
  118: #define PWR_SR1         (PWR_BASE+0x0010)      /* Power status register 1 */
  119: #define PWR_SR2         (PWR_BASE+0x0014)      /* Power status register 2 */
  120: #define PWR_SCR         (PWR_BASE+0x0018)      /* Power status clear register */
  121: #define PWR_PUCRA       (PWR_BASE+0x0020)     /* Power Port A pull-up   control register */
  122: #define PWR_PDCRA       (PWR_BASE+0x0024)     /* Power Port A pull-down control register */
  123: #define PWR_PUCRB       (PWR_BASE+0x0028)     /* Power Port B pull-up   control register */
  124: #define PWR_PDCRB       (PWR_BASE+0x002C)     /* Power Port B pull-down control register */
  125: #define PWR_PUCRC       (PWR_BASE+0x0030)     /* Power Port C pull-up   control register */
  126: #define PWR_PDCRC       (PWR_BASE+0x0034)     /* Power Port C pull-down control register */
  127: #define PWR_PUCRD       (PWR_BASE+0x0038)     /* Power Port D pull-up   control register */
  128: #define PWR_PDCRD       (PWR_BASE+0x003C)     /* Power Port D pull-down control register */
  129: #define PWR_PUCRE       (PWR_BASE+0x0040)     /* Power Port E pull-up   control register */
  130: #define PWR_PDCRE       (PWR_BASE+0x0044)     /* Power Port E pull-down control register */
  131: #define PWR_PUCRF       (PWR_BASE+0x0048)     /* Power Port F pull-up   control register */
  132: #define PWR_PDCRF       (PWR_BASE+0x004C)     /* Power Port F pull-down control register */
  133: #define PWR_PUCRG       (PWR_BASE+0x0050)     /* Power Port G pull-up   control register */
  134: #define PWR_PDCRG       (PWR_BASE+0x0054)     /* Power Port G pull-down control register */
  135: #define PWR_PUCRH       (PWR_BASE+0x0058)     /* Power Port H pull-up   control register */
  136: #define PWR_PDCRH       (PWR_BASE+0x005C)     /* Power Port H pull-down control register */
  137: #define PWR_PUCRI       (PWR_BASE+0x0060)     /* Power Port I pull-up   control register */
  138: #define PWR_PDCRI       (PWR_BASE+0x0064)     /* Power Port I pull-down control register */
  139: 
  140: /* PWR_CR1 bit definition */
  141: #define PWR_CR1_LPR             0x00004000 /* Low-power mode */
  142: 
  143: #define PWR_CR1_VOS             0x00000600 /* Voltage scaling range selection */
  144: #define PWR_CR1_VOS_RANGE1      0x00000200   /*         Range 1 */
  145: #define PWR_CR1_VOS_RANGE2      0x00000400   /*         Range 2 */
  146: 
  147: #define PWR_CR1_DBP             0x00000100 /* Disable backup domain write protection */
  148: #define PWR_CR1_LPMS            0x00000007        /* Low-power mode selection */
  149: #define PWR_CR1_LPMS_STOP0      0x00000000   /*        000 : Stop 0 mode */
  150: #define PWR_CR1_LPMS_STOP1      0x00000001   /*        001 : Stop 1 mode */
  151: #define PWR_CR1_LPMS_STOP2      0x00000002   /*        010 : Stop 2 mode */
  152: #define PWR_CR1_LPMS_STANDBY    0x00000003 /*      011 : Sandby mode */
  153: #define PWR_CR1_LPMS_SHUTDOWN   0x00000004        /*     1xx : Shutdown mo */
  154: 
  155: /* PWR register initial value */
  156: /* PWR_CR1 */
  157: #define PWR_CR1_INIT            (PWR_CR1_VOS_RANGE1) /* set High Performance Range (Range1) */
  158: 
  159: /*
  160:  * RCC (Reset & Clock control) registers
  161:  */
  162: #define RCC_BASE        0x40021000
  163: #define RCC_CR          (RCC_BASE + 0x0000)     /* Clock control register */
  164: #define RCC_ICSCR       (RCC_BASE + 0x0004)   /* Internal clock sources calibration register */
  165: #define RCC_CFGR        (RCC_BASE + 0x0008)    /* Clock configuration register */
  166: #define RCC_PLLCFGR     (RCC_BASE + 0x000C) /* PLL configuration register */
  167: #define RCC_PLLSAI1CFGR (RCC_BASE + 0x0010)     /* PLLSAI1 configuration register */
  168: #define RCC_PLLSAI2CFGR (RCC_BASE + 0x0014)     /* PLLSAI2 configuration register */
  169: #define RCC_CIER        (RCC_BASE + 0x0018)    /* Clock interrupt enable register */
  170: #define RCC_CIFR        (RCC_BASE + 0x001C)    /* Clock interrupt flag register */
  171: #define RCC_CICR        (RCC_BASE + 0x0020)    /* Clock interrupt clear register */
  172: #define RCC_AHB1RSTR    (RCC_BASE + 0x0028)        /* AHB1 peripheral reset register */
  173: #define RCC_AHB2RSTR    (RCC_BASE + 0x002C)        /* AHB2 peripheral reset register */
  174: #define RCC_AHB3RSTR    (RCC_BASE + 0x0030)        /* AHB3 peripheral reset register */
  175: #define RCC_APB1RSTR1   (RCC_BASE + 0x0038)       /* APB1 peripheral reset register 1 */
  176: #define RCC_APB1RSTR2   (RCC_BASE + 0x003C)       /* APB1 peripheral reset register 2 */
  177: #define RCC_APB2RSTR    (RCC_BASE + 0x0040)        /* APB2 peripheral reset register */
  178: #define RCC_AHB1ENR     (RCC_BASE + 0x0048) /* AHB1 peripheral clock enable register */
  179: #define RCC_AHB2ENR     (RCC_BASE + 0x004C) /* AHB2 peripheral clock enable register */
  180: #define RCC_AHB3ENR     (RCC_BASE + 0x0050) /* AHB3 peripheral clock enable register */
  181: #define RCC_APB1ENR1    (RCC_BASE + 0x0058)        /* APB1 peripheral clock enable register 1 */
  182: #define RCC_APB1ENR2    (RCC_BASE + 0x005C)        /* APB1 peripheral clock enable register 2 */
  183: #define RCC_APB2ENR     (RCC_BASE + 0x0060) /* APB2 peripheral clock enable register */
  184: #define RCC_AHB1SMENR   (RCC_BASE + 0x0068)       /* AHB1 peripheral clocks enable in Sleep and Stop modes register */
  185: #define RCC_AHB2SMENR   (RCC_BASE + 0x006C)       /* AHB2 peripheral clocks enable in Sleep and Stop modes register */
  186: #define RCC_AHB3SMENR   (RCC_BASE + 0x0070)       /* AHB3 peripheral clocks enable in Sleep and Stop modes register */
  187: #define RCC_APB1SMENR1  (RCC_BASE + 0x0078)      /* APB1 peripheral clocks enable in Sleep and Stop modes register 1 */
  188: #define RCC_APB1SMENR2  (RCC_BASE + 0x007C)      /* APB1 peripheral clocks enable in Sleep and Stop modes register 2 */
  189: #define RCC_APB2SMENR   (RCC_BASE + 0x0080)       /* APB2 peripheral clocks enable in Sleep and Stop modes register */
  190: #define RCC_CCIPR       (RCC_BASE + 0x0088)   /* Peripherals independent clock configuration register */
  191: #define RCC_BDCR        (RCC_BASE + 0x0090)    /* Backup domain control register */
  192: #define RCC_CSR         (RCC_BASE + 0x0094)    /* Control/status register */
  193: #define RCC_CRRCR       (RCC_BASE + 0x0098)   /* Clock recovery RC register */
  194: #define RCC_CCIPR2      (RCC_BASE + 0x009C)  /* Peripherals independent clock configuration register */
  195: 
  196: /* RCC_CR bit definition */
  197: #define RCC_CR_PLLSAI2RDY       0x20000000    // SAI2 PLL clock ready flag
  198: #define RCC_CR_PLLSAI2ON        0x10000000     // SAI2 PLL enable
  199: #define RCC_CR_PLLSAI1RDY       0x08000000    // SAI1 PLL clock ready flag
  200: #define RCC_CR_PLLSAI1ON        0x04000000     // SAI1 PLL enable
  201: #define RCC_CR_PLLRDY           0x02000000       // Main PLL clock ready flag
  202: #define RCC_CR_PLLON            0x01000000        // Main PLL enable
  203: #define RCC_CR_CSSON            0x00080000        // Clock security system enable
  204: #define RCC_CR_HSEBYP           0x00040000       // HSE crystal oscillator bypass
  205: #define RCC_CR_HSERDY           0x00020000       // HSE clock ready flag
  206: #define RCC_CR_HSEON            0x00010000        // HSE clock enable
  207: #define RCC_CR_HSIASFS          0x00000800      // HSI16 automatic start from Stop
  208: #define RCC_CR_HSIRDY           0x00000400       // HSI16 clock ready flag
  209: #define RCC_CR_HSIKERON         0x00000200     // HSI16 always enable for peripheral kernels.
  210: #define RCC_CR_HSION            0x00000100        // HSI16 clock enable
  211: #define RCC_CR_MSIRANGE         0x000000F0     // MSI clock ranges
  212: #define RCC_CR_MSIRGSEL         0x00000008     // MSI clock range selection
  213: #define RCC_CR_MSIPLLEN         0x00000004     // MSI clock PLL enable
  214: #define RCC_CR_MSIRDY           0x00000002       // MSI clock ready flag
  215: #define RCC_CR_MSION            0x00000001        // MSI clock enable
  216: 
  217: /* MSI clock range value (RCC_CR_MSIRANGE) */
  218: #define RCC_CR_MSIRANGE_100K    0x00000000 //      around 100 KHz
  219: #define RCC_CR_MSIRANGE_200K    0x00000010 //      around 200 KHz
  220: #define RCC_CR_MSIRANGE_400K    0x00000020 //      around 400 KHz
  221: #define RCC_CR_MSIRANGE_800K    0x00000030 //      around 800 KHz
  222: #define RCC_CR_MSIRANGE_1M      0x00000040   //        around   1 MHz
  223: #define RCC_CR_MSIRANGE_2M      0x00000050   //        around   2 MHz
  224: #define RCC_CR_MSIRANGE_4M      0x00000060   //        around   4 MHz
  225: #define RCC_CR_MSIRANGE_8M      0x00000070   //        around   8 MHz
  226: #define RCC_CR_MSIRANGE_16M     0x00000080  //       around  16 MHz
  227: #define RCC_CR_MSIRANGE_24M     0x00000090  //       around  24 MHz
  228: #define RCC_CR_MSIRANGE_32M     0x000000A0  //       around  32 MHz
  229: #define RCC_CR_MSIRANGE_48M     0x000000B0  //       around  48 MHz
  230: 
  231: /* RCC_CFGR bit definition */
  232: #define RCC_CFGR_MCOPRE         0x70000000     // Microcontroller clock output prescaler
  233: #define RCC_CFGR_MCOSEL         0x0F000000     // Microcontroller clock output
  234: #define RCC_CFGR_STOPWUCK       0x00008000    // Wakeup from Stop and CSS backup clock selection
  235: #define RCC_CFGR_PPRE2          0x00003800      // APB high-speed prescaler (APB2)
  236: #define RCC_CFGR_PPRE1          0x00000700      // APB low-speed prescaler (APB1)
  237: #define RCC_CFGR_HPRE           0x000000F0       // AHB prescaler
  238: #define RCC_CFGR_SWS            0x0000000C        // System clock switch status
  239: #define RCC_CFGR_SW             0x00000003 // System clock switch
  240: 
  241: #define RCC_CFGR_SWS_MSI        0x00000000     // MSI used for system clock
  242: #define RCC_CFGR_SWS_HSI16      0x00000004   // HSI16 used for system clock 
  243: #define RCC_CFGR_SWS_HSE        0x00000008     // HSE used for system clock
  244: #define RCC_CFGR_SWS_PLL        0x0000000C     // PLL used for system clock
  245: 
  246: #define RCC_CFGR_SW_MSI         0x00000000     // Use MSI for system clock
  247: #define RCC_CFGR_SW_HSI16       0x00000001    // Use HSI16 for system clock
  248: #define RCC_CFGR_SW_HSE         0x00000002     // Use HSE for system clock
  249: #define RCC_CFGR_SW_PLL         0x00000003     // Use PLL for system clock
  250: 
  251: /* RCC_PLLCFGR bit definition */
  252: #define RCC_PLLCFGR_PLLR        0x06000000     // Main PLL division factor for PLLCLK (system clock)
  253: #define RCC_PLLCFGR_PLLREN      0x01000000   // Main PLL PLLCLK output enable
  254: #define RCC_PLLCFGR_PLLQ        0x00600000     // Main PLL division factor for PLL48M1CLK (48 MHz clock).
  255: #define RCC_PLLCFGR_PLLQEN      0x00100000   // Main PLL PLL48M1CLK output enable
  256: #define RCC_PLLCFGR_PLLP        0x00020000     // Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).
  257: #define RCC_PLLCFGR_PLLPEN      0x00010000   // Main PLL PLLSAI3CLK output enable
  258: #define RCC_PLLCFGR_PLLN        0x00007F00     // Main PLL multiplication factor for VCO
  259: #define RCC_PLLCFGR_PLLM        0x000000F0     // Division factor for the main PLLinput clock
  260: #define RCC_PLLCFGR_PLLSRC      0x00000003   // Main PLL entry clock source
  261: 
  262: /* RCC_APB1ENR1 bit definition */
  263: #define RCC_APB1ENR1_LPTIM1EN   0x80000000        // Low power timer 1 clock enable
  264: #define RCC_APB1ENR1_OPAMPEN    0x40000000 // OPAMP interface clock enable
  265: #define RCC_APB1ENR1_DAC1EN     0x20000000  // DAC1 interface clock enable
  266: #define RCC_APB1ENR1_PWREN      0x10000000   // Power interface clock enable
  267: #define RCC_APB1ENR1_CAN1EN     0x02000000  // CAN1 clock enable
  268: #define RCC_APB1ENR1_CRSEN      0x01000000   // Clock Recovery System clock enable
  269: #define RCC_APB1ENR1_I2C3EN     0x00800000  // I2C3 clock enable
  270: #define RCC_APB1ENR1_I2C2EN     0x00400000  // I2C2 clock enable
  271: #define RCC_APB1ENR1_I2C1EN     0x00200000  // I2C1 clock enable
  272: #define RCC_APB1ENR1_UART5EN    0x00100000 // UART5 clock enable
  273: #define RCC_APB1ENR1_UART4EN    0x00080000 // UART4 clock enable
  274: #define RCC_APB1ENR1_USART3EN   0x00040000        // USART3 clock enable
  275: #define RCC_APB1ENR1_USART2EN   0x00020000        // USART2 clock enable
  276: #define RCC_APB1ENR1_SPI3EN     0x00008000  // SPI3 clock enable
  277: #define RCC_APB1ENR1_SPI2EN     0x00004000  // SPI2 clock enable
  278: #define RCC_APB1ENR1_WWDGEN     0x00000800  // Window watchdog clock enable
  279: #define RCC_APB1ENR1_RTCAPBEN   0x00000400        // RTC APB clock enable
  280: #define RCC_APB1ENR1_TIM7EN     0x00000020  // TIM7 timer clock enable
  281: #define RCC_APB1ENR1_TIM6EN     0x00000010  // TIM6 timer clock enable
  282: #define RCC_APB1ENR1_TIM5EN     0x00000008  // TIM5 timer clock enable
  283: #define RCC_APB1ENR1_TIM4EN     0x00000004  // TIM4 timer clock enable
  284: #define RCC_APB1ENR1_TIM3EN     0x00000002  // TIM3 timer clock enable
  285: #define RCC_APB1ENR1_TIM2EN     0x00000001  // TIM2 timer clock enable
  286: 
  287: /* RCC_APB1ENR2 bit definition */
  288: #define RCC_APB1ENR2_LPTIM2EN   0x00000020        // Low power timer 2 clock enable
  289: #define RCC_APB1ENR2_SWPMI1EN   0x00000004        // Single wire protocol clock enable
  290: #define RCC_APB1ENR2_I2C4EN     0x00000002  // I2C4 clock enable
  291: #define RCC_APB1ENR2_LPUART1EN  0x00000001       // Low power UART 1 clock enable
  292: 
  293: /* RCC_APB2ENR bit definition */
  294: #define RCC_APB2ENR_DFSDM1EN    0x01000000 // DFSDM 1 Timer clock enable
  295: #define RCC_APB2ENR_SAI2EN      0x00400000   // SAI 2 clock enable
  296: #define RCC_APB2ENR_SAI1EN      0x00200000   // SAI1 clock enable
  297: #define RCC_APB2ENR_TIM17EN     0x00040000  // TIM 17 Enable timer clock
  298: #define RCC_APB2ENR_TIM16EN     0x00020000  // TIM16 Enable timer clock
  299: #define RCC_APB2ENR_TIM15EN     0x00010000  // TIM 15 Enable timer clock
  300: #define RCC_APB2ENR_USART1EN    0x00004000 // USART1 clock enable
  301: #define RCC_APB2ENR_TIM8EN      0x00002000   // TIM 8 Timer clock enable
  302: #define RCC_APB2ENR_SPI1EN      0x00001000   // SPI 1 clock enable
  303: #define RCC_APB2ENR_TIM1EN      0x00000800   // TIM1 Enable timer clock
  304: #define RCC_APB2ENR_SDMMC1EN    0x00000400 // Enable SDMMC clock
  305: #define RCC_APB2ENR_FWEN        0x00000080     // Enable Firewall Clock
  306: #define RCC_APB2ENR_SYSCFGEN    0x00000001 // SYSCFG + COMP + VREFBUF clock enable
  307: 
  308: /* RCC_AHB2ENR bit definition */
  309: #define RCC_AHB2ENR_GPIOAEN     0x00000001  // GPIOA clock enable
  310: #define RCC_AHB2ENR_GPIOBEN     0x00000002  // GPIOB clock enable
  311: #define RCC_AHB2ENR_GPIOCEN     0x00000004  // GPIOC clock enable
  312: #define RCC_AHB2ENR_GPIODEN     0x00000008  // GPIOD clock enable
  313: #define RCC_AHB2ENR_GPIOEEN     0x00000010  // GPIOE clock enable
  314: #define RCC_AHB2ENR_GPIOFEN     0x00000020  // GPIOF clock enable
  315: #define RCC_AHB2ENR_GPIOGEN     0x00000040  // GPIOG clock enable
  316: #define RCC_AHB2ENR_GPIOHEN     0x00000080  // GPIOH clock enable
  317: #define RCC_AHB2ENR_GPIOIEN     0x00000100  // GPIOI clock enable
  318: #define RCC_AHB2ENR_ADCEN       0x00002000    // ADC clock enable
  319: 
  320: /* ------------------------------------------------------------------------ */
  321: /*
  322:  * System Timer clock
  323:  */
  324: 
  325: /* Settable interval range (millisecond) */
  326: #define MIN_TIMER_PERIOD        1
  327: #define MAX_TIMER_PERIOD        50
  328: 
  329: 
  330: /* ------------------------------------------------------------------------ */
  331: /*
  332:  * Number of Interrupt vectors
  333:  */
  334: #define N_INTVEC                82    /* Number of Interrupt vectors */
  335: #define N_SYSVEC                16    /* Number of System Exceptions */
  336: 
  337: /*
  338:  * The number of the implemented bit width for priority value fields.
  339:  */
  340: #define INTPRI_BITWIDTH         4
  341: 
  342: 
  343: /* ------------------------------------------------------------------------ */
  344: /*
  345:  * Interrupt Priority Levels
  346:  */
  347: #define INTPRI_MAX_EXTINT_PRI   1 /* Highest Ext. interrupt level */
  348: #define INTPRI_SVC              0   /* SVCall */
  349: #define INTPRI_SYSTICK          1       /* SysTick */
  350: #define INTPRI_PENDSV           15       /* PendSV */
  351: 
  352: /*
  353:  * Time-event handler interrupt level
  354:  */
  355: #define TIMER_INTLEVEL          0
  356: 
  357: /* ------------------------------------------------------------------------ */
  358: /*
  359:  * EXTI (Extended interrupt controller)
  360:  */
  361: #define EXTI_BASE       0x40010400
  362: 
  363: #define EXTI_IMR1       (EXTI_BASE + 0x00)
  364: #define EXTI_EMR1       (EXTI_BASE + 0x04)
  365: #define EXTI_RTSR1      (EXTI_BASE + 0x08)
  366: #define EXTI_FTSR1      (EXTI_BASE + 0x0C)
  367: #define EXTI_SWIER1     (EXTI_BASE + 0x10)
  368: #define EXTI_PR1        (EXTI_BASE + 0x14)
  369: #define EXTI_IMR2       (EXTI_BASE + 0x20)
  370: #define EXTI_EMR2       (EXTI_BASE + 0x24)
  371: #define EXTI_RTSR2      (EXTI_BASE + 0x28)
  372: #define EXTI_FTSR2      (EXTI_BASE + 0x2C)
  373: #define EXTI_SWIER2     (EXTI_BASE + 0x30)
  374: #define EXTI_PR2        (EXTI_BASE + 0x34)
  375: 
  376: /* ------------------------------------------------------------------------ */
  377: /*
  378:  * Watchdog Timer
  379:  */
  380: 
  381: /* ------------------------------------------------------------------------ */
  382: /*
  383:  * GPIO
  384:  */
  385: #define GPIOA_BASE      0x48000000
  386: #define GPIOB_BASE      0x48000400
  387: #define GPIOC_BASE      0x48000800
  388: #define GPIOD_BASE      0x48000C00
  389: #define GPIOE_BASE      0x48001000
  390: #define GPIOF_BASE      0x48000400
  391: #define GPIOG_BASE      0x48000800
  392: #define GPIOH_BASE      0x48000C00
  393: #define GPIOI_BASE      0x48002000
  394: 
  395: #define GPIO_MODER(n)   (GPIO##n##_BASE + 0x00)           /* GPIO port mode register */
  396: #define GPIO_OTYPER(n)  (GPIO##n##_BASE + 0x04)          /* GPIO port output type register */
  397: #define GPIO_OSPEEDR(n) (GPIO##n##_BASE + 0x08)         /* GPIO port output speed register */
  398: #define GPIO_PUPDR(n)   (GPIO##n##_BASE + 0x0C)           /* GPIO port pull-up/pull-down register */
  399: #define GPIO_IDR(n)     (GPIO##n##_BASE + 0x10)             /* GPIO port input data register */
  400: #define GPIO_ODR(n)     (GPIO##n##_BASE + 0x14)             /* GPIO port output data register */
  401: #define GPIO_BSRR(n)    (GPIO##n##_BASE + 0x18)            /* GPIO port bit set/reset register */
  402: #define GPIO_LCKR(n)    (GPIO##n##_BASE + 0x1C)            /* GPIO port configuration lock register */
  403: #define GPIO_AFRL(n)    (GPIO##n##_BASE + 0x20)            /* GPIO alternate function low register */
  404: #define GPIO_AFRH(n)    (GPIO##n##_BASE + 0x24)            /* GPIO alternate function high register */
  405: #define GPIO_BRR(n)     (GPIO##n##_BASE + 0x28)             /* GPIO port bit reset register */
  406: #define GPIO_ASCR(n)    (GPIO##n##_BASE + 0x2C)            /* GPIO port analog switch control register */
  407: 
  408: /* ------------------------------------------------------------------------ */
  409: /*
  410:  * Physical timer (for STM32L4)
  411:  */
  412: #define CPU_HAS_PTMR    (1)
  413: 
  414: /* Timer register definition */
  415: #define TIM2_BASE       0x40000000
  416: #define TIM3_BASE       0x40000400
  417: #define TIM4_BASE       0x40000800
  418: #define TIM5_BASE       0x40000C00
  419: #define TIM6_BASE       0x40001000
  420: #define TIM7_BASE       0x40001400
  421: 
  422: #define TIMxCR1         0x00
  423: #define TIMxCR2         0x04
  424: #define TIMxSMCR        0x08
  425: #define TIMxDIER        0x0C
  426: #define TIMxSR          0x10
  427: #define TIMxEGR         0x14
  428: #define TIMxCCMR1       0x18
  429: #define TIMxCCMR2       0x1C
  430: #define TIMxCCER        0x20
  431: #define TIMxCNT         0x24
  432: #define TIMxPSC         0x28
  433: #define TIMxARR         0x2C
  434: #define TIMxCCR1        0x34
  435: #define TIMxCCR2        0x38
  436: #define TIMxCCR3        0x3C
  437: #define TIMxCCR4        0x40
  438: #define TIMxDCR         0x48
  439: #define TIMxDMAR        0x4C
  440: #define TIMxOR1         0x50
  441: #define TIMxOR2         0x60
  442: 
  443: #define TIMxCR1_CEN     (1<<0)
  444: #define TIMxCR1_OPM     (1<<3)
  445: #define TIMxCR1_DIR     (1<<4)
  446: #define TIMxDIER_UIE    (1<<0)
  447: #define TIMxSR_UIF      (1<<0)
  448: #define TIMxEGR_UG      (1<<0)
  449: 
  450: /* Prescaler value */
  451: #define TIM2PSC_PSC_INIT        0
  452: #define TIM3PSC_PSC_INIT        0
  453: #define TIM4PSC_PSC_INIT        0
  454: #define TIM5PSC_PSC_INIT        0
  455: 
  456: /* Physical timer interrupt number */
  457: #define INTNO_TIM2      28
  458: #define INTNO_TIM3      29
  459: #define INTNO_TIM4      30
  460: #define INTNO_TIM5      50
  461: 
  462: /* Physical timer interrupt priority */
  463: #define INTPRI_TIM2     5
  464: #define INTPRI_TIM3     5
  465: #define INTPRI_TIM4     5
  466: #define INTPRI_TIM5     5
  467: 
  468: /* Phycail timer Maximum count */
  469: #define PTMR_MAX_CNT16    (0x0000FFFF)
  470: #define PTMR_MAX_CNT32    (0xFFFFFFFF)
  471: 
  472: /* ------------------------------------------------------------------------ */
  473: /*
  474:  * Coprocessor
  475:  */
  476: #define CPU_HAS_FPU             1
  477: #define CPU_HAS_DPS             0
  478: 
  479: /*
  480:  *  Number of coprocessors to use. Depends on user configuration
  481:  */
  482: #if USE_FPU
  483: #define NUM_COPROCESSOR         1
  484: #else
  485: #define NUM_COPROCESSOR         0
  486: #endif
  487: 
  488: #endif /* __TK_SYSDEF_DEPEND_CPU_H__ */