gonzui: mtkernel_3/include/sys/sysdepend/cpu/tx03

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      sysdef.h
   16:  *
   17:  *      System dependencies definition (TX03M367 depended)
   18:  *      Included also from assembler program.
   19:  */
   20: 
   21: #ifndef __TK_SYSDEF_DEPEND_CPU_H__
   22: #define __TK_SYSDEF_DEPEND_CPU_H__
   23: 
   24: /*
   25:  **** CPU core-depeneded profile (ARMv7M(ARM Cortex-M3))
   26:  */
   27: 
   28: #include "../core/armv7m/sysdef.h"
   29: 
   30: /* ------------------------------------------------------------------------ */
   31: /*
   32:  * Internal Memorie (Main RAM)  0x20000800 - 0x2001FFFF
   33:  */
   34: #define INTERNAL_RAM_SIZE       0x0001F800
   35: #define INTERNAL_RAM_START      0x20000800
   36: #define INTERNAL_RAM_END        (INTERNAL_RAM_START+INTERNAL_RAM_SIZE)
   37: 
   38: /* ------------------------------------------------------------------------ */
   39: /*
   40:  * Initial Stack pointer (Used in initialization process)
   41:  */
   42: #define INITIAL_SP              INTERNAL_RAM_END
   43: 
   44: 
   45: /* ------------------------------------------------------------------------ */
   46: /*
   47:  * Clock Control
   48:  */
   49: 
   50: /* Clock Generator Registers */
   51: #define CLKCTRL_BASE            0x400F3000
   52: #define CLKCTRL_CGSYSCR         (CLKCTRL_BASE + 0x0000)
   53: #define CLKCTRL_CGOSCCR         (CLKCTRL_BASE + 0x0004)
   54: #define CLKCTRL_CGSTBYCR        (CLKCTRL_BASE + 0x0008)
   55: #define CLKCTRL_CGPLLSEL        (CLKCTRL_BASE + 0x000C)
   56: #define CLKCTRL_CGCKSTP         (CLKCTRL_BASE + 0x0018)
   57: #define CLKCTRL_CGPROTECT       (CLKCTRL_BASE + 0x003C)
   58: 
   59: #define CLKCTRL_CGIMCG          (CLKCTRL_BASE + 0x0040)
   60: #define CLKCTRL_CGIMCGA         (CLKCTRL_BASE + 0x0040)
   61: #define CLKCTRL_CGIMCGB         (CLKCTRL_BASE + 0x0044)
   62: #define CLKCTRL_CGIMCGC         (CLKCTRL_BASE + 0x0048)
   63: #define CLKCTRL_CGIMCGD         (CLKCTRL_BASE + 0x004C)
   64: #define CLKCTRL_CGICRCG         (CLKCTRL_BASE + 0x0060)
   65: 
   66: /* PLL Selection */
   67: #define CLKCTRL_CGPLLSEL_4X             0x00005A0F
   68: #define CLKCTRL_CGPLLSEL_6X             0x00006296
   69: 
   70: #define CLKCTRL_CGPLLSEL_PLLSEL         0x00000001
   71: 
   72: /* Oscillation control */
   73: #define CLKCTRL_CGOSCCR_ALWAYSWRITE     0x00000030
   74: 
   75: #define CLKCTRL_CGOSCCR_WUEON           0x00000001
   76: #define CLKCTRL_CGOSCCR_WUEF            0x00000002
   77: #define CLKCTRL_CGOSCCR_PLLON           0x00000004
   78: #define CLKCTRL_CGOSCCR_WUPSEL_XT1      0x00000008
   79: 
   80: #define CLKCTRL_CGOSCCR_WUPT(usec,freq) ( (usec * freq) >> 4 ) << 20
   81: 
   82: #define MHz                     (UW)(1000000UL)
   83: #define HISPEED_CLOCK_MHz       12
   84: 
   85: #define PLL_MODE_4X             4
   86: #define PLL_MODE_6X             6
   87: 
   88: #define CLOCK_fPLL              (HISPEED_CLOCK_MHz * PLL_MODE_6X * MHz)
   89: #define CLOCK_fc                (CLOCK_fPLL)
   90: #define CLOCK_fgear             (CLOCK_fc / 2)
   91: #define CLOCK_fsys              (CLOCK_fgear)
   92: #define CLOCK_fperiph           (CLOCK_fgear)
   93: #define CLOCK_T0                (CLOCK_fperiph)
   94: 
   95: #define TMCLK                   (CLOCK_fsys / MHz)      /* Timer clock input (MHz) */
   96: #define TMCLK_KHz               (CLOCK_fsys / 1000)  /* Timer clock input (kHz) */
   97: 
   98: /*
   99:  * Settable interval range (millisecond)
  100:  */
  101: #define MIN_TIMER_PERIOD        1
  102: #define MAX_TIMER_PERIOD        50
  103: 
  104: 
  105: /* ------------------------------------------------------------------------ */
  106: /*
  107:  * Number of Interrupt vectors
  108:  */
  109: #define N_INTVEC                128   /* Number of Interrupt vectors */
  110: #define N_SYSVEC                16    /* Number of System Exceptions */
  111: 
  112: /*
  113:  * The number of the implemented bit width for priority value fields.
  114:  */
  115: #define INTPRI_BITWIDTH         3
  116: 
  117: 
  118: /* ------------------------------------------------------------------------ */
  119: /*
  120:  * Interrupt Priority Levels
  121:  */
  122: #define INTPRI_MAX_EXTINT_PRI   1 /* Highest Ext. interrupt level */
  123: #define INTPRI_SVC              0   /* SVCall */
  124: #define INTPRI_SYSTICK          1       /* SysTick */
  125: #define INTPRI_PENDSV           7        /* PendSV */
  126: 
  127: /*
  128:  * Time-event handler interrupt level
  129:  */
  130: #define TIMER_INTLEVEL          0
  131: 
  132: 
  133: /* ------------------------------------------------------------------------ */
  134: /*
  135:  * Watchdog Timer
  136:  */
  137: #define WDOG_BASE               0x400F2000
  138: 
  139: #define WDOG_WDMOD              (WDOG_BASE + 0x0000)        /* Mode Reg. */
  140: #define WDOG_WDCR               (WDOG_BASE + 0x0004) /* Control Reg. */
  141: 
  142: #define WDOG_WDMOD_WDTE         0x00000080     /* Enable */
  143: #define WDOG_WDCR_DISABLE       0x000000B1    /* Disable Code */
  144: 
  145: 
  146: /* ------------------------------------------------------------------------ */
  147: /*
  148:  * GPIO
  149:  */
  150: #define PORTA_BASE      0x400C0000
  151: #define PORTB_BASE      0x400C0100
  152: #define PORTE_BASE      0x400C0400
  153: #define PORTF_BASE      0x400C0500
  154: #define PORTG_BASE      0x400C0600
  155: #define PORTH_BASE      0x400C0700
  156: #define PORTI_BASE      0x400C0800
  157: #define PORTK_BASE      0x400C0A00
  158: #define PORTL_BASE      0x400C0B00
  159: 
  160: #define PORT_DATA(n)    (PORT##n##_BASE + 0x00)    // data
  161: #define PORT_CR(n)      (PORT##n##_BASE + 0x04)      // Output Control
  162: #define PORT_FR1(n)     (PORT##n##_BASE + 0x08)     // Function 1
  163: #define PORT_FR2(n)     (PORT##n##_BASE + 0x0C)     // Function 2
  164: #define PORT_FR3(n)     (PORT##n##_BASE + 0x10)     // Function 3
  165: #define PORT_FR4(n)     (PORT##n##_BASE + 0x14)     // Function 4
  166: #define PORT_FR5(n)     (PORT##n##_BASE + 0x18)     // Function 5
  167: #define PORT_FR6(n)     (PORT##n##_BASE + 0x1C)     // Function 6
  168: #define PORT_OD(n)      (PORT##n##_BASE + 0x28)      // Open Drain Control
  169: #define PORT_PUP(n)     (PORT##n##_BASE + 0x2C)     // Pull-up Control
  170: #define PORT_PDN(n)     (PORT##n##_BASE + 0x30)     // Pull-down Control
  171: #define PORT_IE(n)      (PORT##n##_BASE + 0x38)      // Input Control
  172: 
  173: /* ------------------------------------------------------------------------ */
  174: /*
  175:  * Physical timer (for TX03M67 TMRB)
  176:  */
  177: #define CPU_HAS_PTMR    (1)
  178: 
  179: /* TMRB Register definition */
  180: #define TMRB0_BASE      0x400C4000
  181: #define TMRB1_BASE      0x400C4100
  182: #define TMRB2_BASE      0x400C4200
  183: #define TMRB3_BASE      0x400C4300
  184: #define TMRB4_BASE      0x400C4400
  185: #define TMRB5_BASE      0x400C4500
  186: #define TMRB6_BASE      0x400C4600
  187: #define TMRB7_BASE      0x400C4700
  188: 
  189: #define TBxEN           0x0000
  190: #define TBxRUN          0x0004
  191: #define TBxCR           0x0008
  192: #define TBxMOD          0x000C
  193: #define TBxFFCR         0x0010
  194: #define TBxST           0x0014
  195: #define TBxIM           0x0018
  196: #define TBxUC           0x001C
  197: #define TBxRG0          0x0020
  198: #define TBxRG1          0x0024
  199: #define TBxCP0          0x0028
  200: #define TBxCP1          0x002C
  201: 
  202: #define TBxEN_TBEN      (1<<7)
  203: #define TBxRUN_TBRUN    (1<<0)
  204: #define TBxRUN_TBPRUN   (1<<2)
  205: #define TBxFFCR_TDE     (0x000000C3)
  206: #define TBxMOD_TBCLE    (1<<3)
  207: #define TBxIM_TBIMOF    (1<<2)
  208: #define TBxIM_TBIM1     (1<<1)
  209: #define TBxIM_TBIM0     (1<<0)
  210: 
  211: /* Physical timer clock */
  212: #define TB0MOD_TBCLK    (0x00000001)    // Source clock = T1
  213: #define TB1MOD_TBCLK    (0x00000001)    // Source clock = T1
  214: #define TB2MOD_TBCLK    (0x00000001)    // Source clock = T1
  215: #define TB3MOD_TBCLK    (0x00000001)    // Source clock = T1
  216: #define TB4MOD_TBCLK    (0x00000001)    // Source clock = T1
  217: #define TB5MOD_TBCLK    (0x00000001)    // Source clock = T1
  218: #define TB6MOD_TBCLK    (0x00000001)    // Source clock = T1
  219: #define TB7MOD_TBCLK    (0x00000001)    // Source clock = T1
  220: 
  221: /* Physical timer interrupt number */
  222: #define INTNO_TMRB0     75
  223: #define INTNO_TMRB1     78
  224: #define INTNO_TMRB2     81
  225: #define INTNO_TMRB3     84
  226: #define INTNO_TMRB4     87
  227: #define INTNO_TMRB5     90
  228: #define INTNO_TMRB6     93
  229: #define INTNO_TMRB7     96
  230: 
  231: /* Physical timer interrupt priority */
  232: #define INTPRI_TMRB0    5
  233: #define INTPRI_TMRB1    5
  234: #define INTPRI_TMRB2    5
  235: #define INTPRI_TMRB3    5
  236: #define INTPRI_TMRB4    5
  237: #define INTPRI_TMRB5    5
  238: #define INTPRI_TMRB6    5
  239: #define INTPRI_TMRB7    5
  240: 
  241: /* Phycail timer Maximum count */
  242: #define PTMR_MAX_CNT    (0x0000FFFF)
  243: 
  244: 
  245: /* ------------------------------------------------------------------------ */
  246: /*
  247:  * Coprocessor
  248:  */
  249: #define CPU_HAS_FPU                     0
  250: #define CPU_HAS_DPS                     0
  251: 
  252: /*
  253:  *  Number of coprocessors to use. 
  254:  *    There is no coprocessor for this microcomputer.
  255:  */
  256: #define NUM_COPROCESSOR         0
  257: 
  258: #endif /* __TK_SYSDEF_DEPEND_CPU_H__ */