mtkernel_3/include/sys/sysdepend/iote_stm32l4/sysdef.h | bare source | permlink (0.00 seconds) |
1: /* 2: *---------------------------------------------------------------------- 3: * micro T-Kernel 3.00.03 4: * 5: * Copyright (C) 2006-2021 by Ken Sakamura. 6: * This software is distributed under the T-License 2.2. 7: *---------------------------------------------------------------------- 8: * 9: * Released by TRON Forum(http://www.tron.org) at 2021/03/31. 10: * 11: *---------------------------------------------------------------------- 12: */ 13: 14: /* 15: * sysdef.h 16: * 17: * System dependencies definition (STM32L4 IoT-Engine depended) 18: * Included also from assembler program. 19: */ 20: 21: #ifndef __SYS_SYSDEF_DEPEND_H__ 22: #define __SYS_SYSDEF_DEPEND_H__ 23: 24: 25: /* CPU-dependent definition */ 26: #include "../cpu/stm32l4/sysdef.h" 27: 28: /* ------------------------------------------------------------------------ */ 29: /* 30: * Clock control definition 31: */ 32: 33: /* RCC register initial value */ 34: #define RCC_CFGR_INIT (0x00000000) // SYSCLK = PLL ,SYSCLK,HCLK not divided. 35: #define RCC_PLLCFGR_INIT (0x00002810) // M = 2, N = 40, P = 7, Q = 2, R =2 36: #define RCC_PLLSAI1CFGR_INIT (0x00002000) // N = 32, P = 7, Q = 2, R =2 37: #define RCC_PLLSAI2CFGR_INIT (0x00001000) // N = 16, P = 7, Q = 2, R =2 38: 39: /* Clock frequency */ 40: #define SYSCLK (80) /* System clock */ 41: #define HCLK (SYSCLK) /* Peripheral clock (AHB) */ 42: #define PCLK1 (HCLK) /* Peripheral clock (APB1) */ 43: #define PCLK2 (HCLK) /* Peripheral clock (APB2) */ 44: #define TMCLK (HCLK) /* System timer clock input (MHz) */ 45: #define TMCLK_KHz (TMCLK * 1000) /* System timer clock input (kHz) */ 46: 47: /* ------------------------------------------------------------------------ */ 48: /* 49: * Maximum value of Power-saving mode switching prohibition request. 50: * Used in tk_set_pow API. 51: */ 52: #define LOWPOW_LIMIT 0x7fff /* Maximum number for disabling */ 53: 54: 55: #endif /* __TK_SYSDEF_DEPEND_H__ */