gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *      syslib.h
   16:  *
   17:  *      micro T-Kernel System Library  (RZ/A2M depended)
   18:  */
   19: 
   20: #ifndef __TK_SYSLIB_CPU_DEPEND_H__
   21: #define __TK_SYSLIB_CPU_DEPEND_H__
   22: 
   23: #include "../core/armv7a/syslib.h"
   24: 
   25: /* ------------------------------------------------------------------------ */
   26: /*
   27:  * Interrupt Control
   28:  */
   29: 
   30: /*
   31:  * Interrupt number
   32:  */
   33: 
   34: /*
   35:  * Interrupt mode ( Use SetIntMode )
   36:  */
   37: #define IM_LEVEL        0x00   /* high level detection */
   38: #define IM_EDGE         0x01   /* Rising edge detection */
   39: 
   40: /* ------------------------------------------------------------------------ */
   41: /*
   42:  * I/O port access
   43:  *      for memory mapped I/O
   44:  */
   45: Inline void out_w( UW port, UW data )
   46: {
   47:         *(_UW*)port = data;
   48: }
   49: Inline void out_h( UW port, UH data )
   50: {
   51:         *(_UH*)port = data;
   52: }
   53: Inline void out_b( UW port, UB data )
   54: {
   55:         *(_UB*)port = data;
   56: }
   57: 
   58: Inline UW in_w( UW port )
   59: {
   60:         return *(_UW*)port;
   61: }
   62: Inline UH in_h( UW port )
   63: {
   64:         return *(_UH*)port;
   65: }
   66: Inline UB in_b( UW port )
   67: {
   68:         return *(_UB*)port;
   69: }
   70: 
   71: Inline void and_w( UW port, UW data)
   72: {
   73:         *(_UW*)port &= data;
   74: }
   75: Inline void and_h( UW port, UH data)
   76: {
   77:         *(_UH*)port &= data;
   78: }
   79: Inline void and_b( UW port, UB data)
   80: {
   81:         *(_UB*)port &= data;
   82: }
   83: 
   84: Inline void or_w( UW port, UW data)
   85: {
   86:         *(_UW*)port |= data;
   87: }
   88: Inline void or_h( UW port, UH data)
   89: {
   90:         *(_UH*)port |= data;
   91: }
   92: Inline void or_b( UW port, UB data)
   93: {
   94:         *(_UB*)port |= data;
   95: }
   96: 
   97: #endif /* __TK_SYSLIB_DEPEND_H__ */