gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_CORE_ARMV7A
   16: 
   17: /*
   18:  *      interrupt.c  (ARMv7-A)
   19:  *      Interrupt control
   20:  */
   21: 
   22: #include <kernel.h>
   23: #include "../../../sysdepend.h"
   24: 
   25: /* Interrupt vector table */
   26: Noinit(EXPORT FP knl_intvec_tbl[N_INTVEC]);
   27: 
   28: /* High level programming language interrupt handler table */
   29: Noinit(EXPORT FP knl_hll_inthdr_tbl[N_INTVEC]);
   30: 
   31: /* SVC handler table */
   32: EXPORT const FP knl_svcvec_tbl[N_SVCHDR] = {
   33:         NULL, NULL, NULL, NULL, NULL, NULL,    /* 0 ~ 5 : reserved. */
   34:         NULL,                                  /* 6 : micro T-Kernel system call */
   35:         knl_dispatch_to_schedtsk,              /* 7 : force dispatch */
   36:         knl_dispatch_entry,                    /* 8 : task dispatcher */
   37:         NULL,                                  /* 9 : debug support function */
   38:         NULL                                   /* 10: Extended SVC */
   39: };
   40: 
   41: /* ----------------------------------------------------------------------- */
   42: /*
   43:  * Set interrupt handler (Used in tk_def_int())
   44:  */
   45: EXPORT ER knl_define_inthdr( INT intno, ATR intatr, FP inthdr )
   46: {
   47:         if((inthdr != NULL) && ((intatr & TA_HLNG) != 0 )) {
   48:                 knl_hll_inthdr_tbl[intno] = inthdr;
   49:                 inthdr = knl_hll_inthdr;
   50:         }
   51:         knl_intvec_tbl[intno] = inthdr;
   52: 
   53:         return E_OK;
   54: }
   55: 
   56: /* ------------------------------------------------------------------------ */
   57: /*
   58:  * Interrupt initialize
   59:  */
   60: 
   61:  /* GICD_ICFGR(n) Register default value */
   62: LOCAL const UW GICD_ICFGR_inival[] =
   63: {                               //           Interrupt ID
   64:         0xAAAAAAAAuL,          // GICD_ICFGR0  :  15 to   0
   65:         0x55540000uL,          // GICD_ICFGR1  :  19 to  16
   66:         0xFD555555uL,          // GICD_ICFGR2  :  47 to  32
   67:         0x7FFFFFFFuL,          // GICD_ICFGR3  :  63 to  48
   68:         0x55555555uL,          // GICD_ICFGR4  :  79 to  64
   69:         0xD57F5555uL,          // GICD_ICFGR5  :  95 to  80
   70:         0xFFFFFFFFuL,          // GICD_ICFGR6  : 111 to  96
   71:         0xFFFFFFFFuL,          // GICD_ICFGR7  : 127 to 112
   72:         0xFFFFFFFFuL,          // GICD_ICFGR8  : 143 to 128
   73:         0xFFFFFFFFuL,          // GICD_ICFGR9  : 159 to 144
   74:         0xFFFFFFFFuL,          // GICD_ICFGR10 : 175 to 160
   75:         0xFFFFFFFFuL,          // GICD_ICFGR11 : 191 to 176
   76:         0xFFFFFFFFuL,          // GICD_ICFGR12 : 207 to 192
   77:         0xFFFFFFFFuL,          // GICD_ICFGR13 : 223 to 208
   78:         0xFFFFFFFFuL,          // GICD_ICFGR14 : 239 to 224
   79:         0x7D5FD57FuL,          // GICD_ICFGR15 : 255 to 240
   80:         0x557D7DDFuL,          // GICD_ICFGR16 : 271 to 256
   81:         0x557D557DuL,          // GICD_ICFGR17 : 287 to 272
   82:         0x5555557DuL,          // GICD_ICFGR18 : 303 to 288
   83:         0x55555555uL,          // GICD_ICFGR19 : 319 to 304
   84:         0xF5555555uL,          // GICD_ICFGR20 : 335 to 320
   85:         0x5555FFFFuL,          // GICD_ICFGR21 : 351 to 336
   86:         0x55555555uL,          // GICD_ICFGR22 : 367 to 352
   87:         0xFFDD5555uL,          // GICD_ICFGR23 : 383 to 368
   88:         0xFFFFFFFFuL,          // GICD_ICFGR24 : 399 to 384
   89:         0xFFFFFFFFuL,          // GICD_ICFGR25 : 415 to 400
   90:         0xFFFFFFFFuL,          // GICD_ICFGR26 : 431 to 416
   91:         0x5FFFFFDFuL,          // GICD_ICFGR27 : 447 to 432
   92:         0x55555555uL,          // GICD_ICFGR28 : 463 to 448
   93:         0x55555555uL,          // GICD_ICFGR29 : 479 to 464
   94:         0x55555555uL,          // GICD_ICFGR30 : 495 to 480
   95:         0x55555555uL,          // GICD_ICFGR31 : 511 to 496
   96: };
   97: 
   98: EXPORT ER knl_init_interrupt( void )
   99: {
  100:         INT    i;
  101:         _UW    *reg;
  102: 
  103:         /* Initialization of interrupt vector table */
  104:         for(i = 0; i < N_INTVEC; i++) knl_intvec_tbl[i] = (FP)NULL;
  105: 
  106:         /* Register exception handler used on OS */
  107:         knl_define_inthdr(INTNO_SYSTICK, TA_HLNG, (FP)knl_timer_handler);      /* System Timer Interruput */
  108: 
  109:         /* GIC initialization */
  110:         reg = (_UW*)GICD_IGROUPR(0);
  111:         for (i = 0; i < GICD_IGROUPR_N; i++) {
  112:                 reg[i] = 0x00000000uL;                /* All interrupts are Group 0 */
  113:         }
  114: 
  115:         reg = (_UW*)GICD_ICFGR(0);
  116:         for (i = 0; i < GICD_ICFGR_N; i++) {
  117:                 reg[i] = GICD_ICFGR_inival[i];        /* Copy from the default table */
  118:         }
  119: 
  120:         reg = (_UW*)GICD_IPRIORITYR(0);
  121:         for (i = 0; i < GICD_IPRIORITYR_N; i++) {
  122:                 reg[i] = 0xF8F8F8F8uL;                /* All priorities are 31 */
  123:         }
  124: 
  125:         reg = (_UW*)GICD_ITARGETR(0);
  126:         for (i = 8; i < GICD_ITARGETR_N; i++) {
  127:                 reg[i] = 0x01010101uL;                /* Target processor is CPU-0 */
  128:         }
  129:         
  130:         reg = (_UW*)GICD_ICENABLER(0);
  131:         for (i = 0; i < GICD_ICENABLER_N; i++) {
  132:                 reg[i] = 0xFFFFFFFFuL;
  133:         }
  134: 
  135:         out_w(GICC_PMR, 31<<3);                        /* Allow all interrupts */
  136:         out_w(GICC_BPR, 0x00000002UL);
  137:         out_w(GICC_CTLR, 0x00000003UL);
  138:         out_w(GICD_CTLR, 0x00000001uL);
  139: 
  140:         return E_OK;
  141: }
  142: 
  143: #endif /* CPU_CORE_ARMV7A */