1: /*
2: *----------------------------------------------------------------------
3: * micro T-Kernel 3.00.05
4: *
5: * Copyright (C) 2006-2021 by Ken Sakamura.
6: * This software is distributed under the T-License 2.2.
7: *----------------------------------------------------------------------
8: *
9: * Released by TRON Forum(http://www.tron.org) at 2021/11.
10: *
11: *----------------------------------------------------------------------
12: */
13:
14: #include <sys/machine.h>
15: #ifdef CPU_CORE_ARMV7A
16:
17: /*
18: * reset_hdl.S (ARMv7-A)
19: * Reset handler
20: */
21:
22: #define _in_asm_source_
23: #include <sys/sysdef.h>
24: #include <sys/knldef.h>
25:
26: .section RESET_HANDLER, "ax"
27: .arm
28:
29: /* ---------------------------------------------------------------------------------
30: *
31: * Reset Handler
32: */
33: .weak start
34: start:
35: .global Csym(Reset_Handler)
36:
37: .extern Csym(startup_clock)
38: .extern Csym(vector_table)
39: .extern Csym(knl_init_ttb)
40: .extern Cstm(reset_main)
41:
42: Csym(Reset_Handler):
43: /* Disable IRQ */
44: mrs r0, cpsr
45: orr r0, r0, #PSR_DI
46: msr cpsr_c, r0
47:
48: /* Disable cache & MMU */
49: MRC p15, 0, r0, c1, c0, 0 // Read CP15 System Control register (SCTLR)
50: BIC r0, r0, #CP15_SCTLR_I // Clear I bit to disable I Cache
51: BIC r0, r0, #CP15_SCTLR_C // Clear C bit to disable D Cache
52: BIC r0, r0, #CP15_SCTLR_M // Clear M bit to disable MMU
53: BIC r0, r0, #CP15_SCTLR_V // Clear V bit to VBAR vector
54: MCR p15, 0, r0, c1, c0, 0 // Write value back to CP15 System Control register (SCTLR)
55: ISB // Instruction Synchronization barrier
56:
57: /* Set VBAR */
58: ldr r0, =Csym(vector_table)
59: mcr p15, 0, r0, c12, c0, 0
60:
61: /* Set stack pointer */
62: cps #PSR_SVC // SVC Mode **** uT-Kernel typically use SVC mode ****
63: ldr sp, =__tmp_stack_start
64:
65: /* CPG settings */
66: // bl Csym(startup_clock) // (CPU depended part)/cpu_clock.c
67:
68: /* Invalidate TLB */
69: mov r0,#0
70: mcr p15, 0, r0, c8, c7, 0
71:
72: /* Invalidate I-cache, flushes BTAC */
73: mov r0, #0
74: mcr p15, 0, r0, c7, c5, 0
75:
76: /* Invalidate D-Caches */
77: mov r2, #4
78: dc_loop1: // loop of way
79: mov r1, #256 // # of set
80: sub r0, r2, #1 // current way
81: mov r0, r0, lsl #30
82: dc_loop2: // loop of set
83: mcr p15, 0, r0, c7, c6, 2 // invalidate by set/way
84: add r0, r0, #0x20
85: subs r1, r1, #1
86: bne dc_loop2
87: subs r2, r2, #1
88: bne dc_loop1
89:
90: /* TTB initialize */
91: bl init_ttb
92:
93: /* domain access control register */
94: mrc p15, 0, r0, c3, c0, 0 // Read CP15 Domain Access Control Register (DACR)
95: ldr r0, =0x55555555 // Initialize every domain entry to b01 (client)
96: mcr p15, 0, r0, c3, c0, 0 // Write CP15 Domain Access Control Register (DACR)
97:
98: /* enable MMU (cache not yet) */
99: mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register (SCTLR)
100: bic r0, r0, #CP15_SCTLR_I // Clear I bit to disable I Cache
101: bic r0, r0, #CP15_SCTLR_C // Clear C bit to disable D Cache
102: bic r0, r0, #CP15_SCTLR_A // Clear A bit to disable strict alignment fault checking
103: orr r0, r0, #CP15_SCTLR_M // Set M bit to enable MMU before scatter loading
104: mcr p15, 0, r0, c1, c0, 0 // Write CP15 System Control register (SCTLR)
105: isb // Instruction Synchronization barrier
106:
107: #if USE_FPU
108: // setting NEON/VFP
109: fpu_init:
110: mrc p15, 0, r0, c1, c0, 2 // Read CP15 Coprocessor Access Control Register(CPACR)
111: orr r0, r0, #(0xf << 20) // CP10/CP11 access enable
112: bic r0, r0, #(3 << 30) // clear ASEDIS/D32DIS bit (SIMD extention enable/d16-d31 access enable)
113: mcr p15, 0, r0, c1, c0, 2 // write CP15 Coprocessor Access Control Register(CPACR)
114: isb // Instruction Synchronization barrier
115: mov r0, #0x40000000 // enable VFP
116: vmsr fpexc, r0 // Write Floating-Point Exception Control register(FPEXC)
117: #endif // USE_FPU
118:
119: bl Csym(reset_main) // Jump to Reset handler Main routine (reset_main.c)
120:
121: terminate: // infinite loop
122: b terminate
123:
124:
125:
126: /* ---------------------------------------------------------------------------------
127: * TTB(translation table base) initialize
128: */
129: #define PAGESIZE_SECTION 0x00100000 /* 1MB size */
130: #define ADDRMASK_SECTION 0xfff00000 /* Bit Mask for 1MB page address. */
131:
132: .extern Csym(knl_ttb_ini) // (CPU depended part)/ttb_ini.c
133: init_ttb:
134: mov r0, #0x0
135: mcr p15, 0, r0, c2, c0, 2 // Write CP15 TTBCR
136:
137: // Set the base address of the page table in TTB register 0
138: ldr r0, =__ttb_area_top
139: mov r1, #0x08 // RGN=b01 (outer cacheable write-back cached, write allocate)
140: // S=0 (translation table walk to non-shared memory)
141: orr r1, r1, #0x40 // IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate)
142: orr r0, r0, r1
143: mcr p15, 0, r0, c2, c0, 0 // Write CP15 TTBR0 (Translation Table Base Register 0)
144:
145: // Clear descriptor area
146: mov r2, #0
147: mov r3, #0
148: mov r4, #0
149: mov r5, #0
150: mov r6, #0
151: mov r7, #0
152: mov r8, #0
153: mov r9, #0
154:
155: ldr r0, =__ttb_area_top
156: ldr r1, =__ttb_area_bottom
157: desc_clr_loop:
158: stmia r0!, {r2-r9} // ZERO clear
159: cmp r0, r1
160: blo desc_clr_loop
161:
162: // Set descriptor area
163: ldr r0, =__ttb_area_top
164: ldr r9, =Csym(knl_ttb_ini)
165: desc_set_loop:
166: ldr r1, [r9, #0x00] // address
167: ldr r2, [r9, #0x04] // size
168: ldr r3, [r9, #0x08] // attribute
169: cmp r2, #0 // if size == 0
170: bxeq lr
171: add r9, #0x10 // update pointer
172:
173: ldr r5, =ADDRMASK_SECTION // Mask address
174: and r1, r1, r5
175: add r4, r0, r1, lsr #(20-2) // r4: Descriptor address(base+Logical address/1M*4)
176:
177: loop_secdesc:
178: orr r6, r1, r3 // Descriptor Set value
179: str r6, [r4], #4 // Write setting value (with pointer update)
180:
181: add r1, r1, #PAGESIZE_SECTION // Address update
182: subs r2, r2, #PAGESIZE_SECTION // Remaining size update
183: bhi loop_secdesc // Loop if size is greater than 0
184:
185: b desc_set_loop
186:
187: /* ---------------------------------------------------------------------------------
188: * L1 D/I cache enable
189: */
190: .global Csym(L1CacheInit)
191: Csym(L1CacheInit):
192: // enable MMU, D/I-cache, branch prediction
193: mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register (SCTLR)
194: orr r0, r0, #CP15_SCTLR_I // Set I bit to dnable I Cache
195: orr r0, r0, #CP15_SCTLR_C // Set C bit to enable D Cache
196: orr r0, r0, #CP15_SCTLR_Z // Set Z bit to enable Program Flow Prediction
197: mcr p15, 0, r0, c1, c0, 0 // Write CP15 System Control register (SCTLR)
198: isb // Instruction Synchronization barrier
199:
200: // enable Dside prefetch
201: mrc p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register(ACTLR)
202: orr r0, r0, #CP15_ACTLR_DPF // Enable Dside prefetch
203: mcr p15, 0, r0, c1, c0, 1 // Weite CP15 Auxiliary Control Register(ACTLR)
204: isb // Instruction Synchronization barrier
205:
206: bx lr
207:
208: /* ---------------------------------------------------------------------------------
209: * Temporary Stack Area
210: */
211: .section .tmp_stack_section, "aw", %nobits
212: .global __tmp_stack
213: __tmp_stack:
214: .space TMP_STACK_SIZE
215:
216: #endif /* CPU_CORE_ARMV7A */