1: /*
2: *----------------------------------------------------------------------
3: * micro T-Kernel 3.00.05
4: *
5: * Copyright (C) 2006-2021 by Ken Sakamura.
6: * This software is distributed under the T-License 2.2.
7: *----------------------------------------------------------------------
8: *
9: * Released by TRON Forum(http://www.tron.org) at 2021/11.
10: *
11: *----------------------------------------------------------------------
12: */
13:
14: #include <sys/machine.h>
15: #ifdef CPU_CORE_ARMV7A
16:
17: /*
18: * vector_tbl.S (ARMv7-A)
19: * Exception Vector Table
20: */
21:
22: .section VECTOR_TABLE, "ax"
23: .arm
24:
25: /* ---------------------------------------------------------------------------------
26: * Exception Vector Table
27: */
28: .global _PowerON_Reset
29: _PowerON_Reset: // Power-on reset entry point
30:
31: .global Csym(vector_table)
32: .extern Csym(Reset_Handler)
33: .extern Csym(undef_entry)
34: .extern Csym(svc_entry)
35: .extern Csym(iabort_entry)
36: .extern Csym(dabort_entry)
37: .extern Csym(irq_entry)
38: .extern Csym(fiq_entry)
39:
40: Csym(vector_table):
41: ldr pc, =Csym(Reset_Handler) // 0x0000 : Reset exception
42: ldr pc, =Csym(undef_entry) // 0x0004 : Undefined instructions exception
43: ldr pc, =Csym(svc_entry) // 0x0008 : Software interrupts exceptions
44: ldr pc, =Csym(iabort_entry) // 0x000c : Prefetch abort exception
45: ldr pc, =Csym(dabort_entry) // 0x0010 : Data abort exception
46: nop // 0x0014 : Reserved
47: ldr pc, =Csym(irq_entry) // 0x0018 : IRQ exception
48: ldr pc, =Csym(fiq_entry) // 0x001c : FIQ exception
49:
50: #endif /* CPU_CORE_ARMV7A */