1: /*
2: *----------------------------------------------------------------------
3: * micro T-Kernel 3.00.01
4: *
5: * Copyright (C) 2006-2020 by Ken Sakamura.
6: * This software is distributed under the T-License 2.2.
7: *----------------------------------------------------------------------
8: *
9: * Released by TRON Forum(http://www.tron.org) at 2020/05/29.
10: *
11: *----------------------------------------------------------------------
12: */
13:
14: #include <sys/machine.h>
15: #ifdef CPU_CORE_RXV2
16: /*
17: * int_asm.S (RXv2)
18: * Interrupt control assembler routine
19: */
20: #define _in_asm_source_
21:
22: #include <sys/sysdef.h>
23:
24: .section .text
25: .globl Csym(knl_hll_inthdr)
26: .globl Csym(knl_return_inthdr)
27:
28: /* ------------------------------------------------------------------------ */
29: /*
30: * HLL(High level programming language) Interrupt Handler
31: *
32: */
33: .extern Csym(knl_hll_inthdr_ram)
34: .extern Csym(knl_taskindp)
35: .extern Csym(knl_int_nest)
36: .extern Csym(ret_int_dispatch)
37:
38: Csym(knl_hll_inthdr):
39: /* During interrupt disable PSW.I=0 */
40: pushm r14-r15 /* R1-R2 are already saved */
41: pushm r3-r7
42:
43: #if USE_FPU
44: mvfc fpsw, r3
45: push.l r3
46: #endif
47:
48: mov.l #Csym(knl_taskindp), r6 /* enter task independent mode */
49: mov.l [r6], r7
50: add #1, r7
51: mov.l r7, [r6]
52:
53: mov.l #Csym(knl_int_nest), r4 /* interrupt nest count */
54: mov.l [r4], r3
55: mov.l r3, r6
56: add #1, r3
57: mov.l r3, [r4]
58:
59: cmp #0, r6
60: bne l_no_change_sp /* multiple interrupt */
61: mov.l r0, r3
62: mov.l #INTSTACK_TOP, r0 /* change to ISP */
63: mov.l r3, [-r0] /* SSP save */
64: l_no_change_sp:
65:
66: setpsw I /* Interrupt enable */
67:
68: #if USE_STATIC_IVT
69: mov.l #Csym(knl_hll_inthdr_rom), r2 /* call knl_hll_inthdr_rom[n](dintno) */
70: #else
71: mov.l #Csym(knl_hll_inthdr_ram), r2 /* call knl_hll_inthdr_rom[n](dintno) */
72: #endif
73: mov.l [r1, r2], r4 /* r1 is dintno. */
74: jsr r4
75:
76: clrpsw I /* Interrupt disable */
77:
78: ; During interrupt disable PSW.I=0
79: cmp #0, r6
80: bne l_no_change_sp2 /* multiple interrupt */
81:
82: mov.l [r0+], r3 /* r3 = SSP */
83: mov.l r3, r0
84: l_no_change_sp2:
85: sub #1, r7
86: mov.l #Csym(knl_taskindp), r6
87: mov.l r7, [r6]
88:
89: #if USE_FPU
90: pop r3
91: mvtc r3, fpsw
92: #endif
93: popm r3-r7
94: popm r14-r15
95:
96: /* bra Cym(knl_return_inthdr) */
97:
98: /* ------------------------------------------------------------------------ */
99: /*
100: * knl_return_inthdr() Called from tk_ret_int call.
101: * This call can be called only from a handler with the assembler attribute.
102: */
103: Csym(knl_return_inthdr):
104: /* During interrupt disable PSW.I=0 */
105: mov.l #Csym(knl_int_nest), r1 /* Is it a nesting interrupt? */
106: mov.l [r1], r2
107: sub #1, r2
108: mov.l r2, [r1]
109: bne l_nodispatch
110:
111: mov.l #Csym(knl_dispatch_disabled), r1 /* Is it during dispatch disable? */
112: mov.l [r1], r1
113: cmp #0, r1
114: bne l_nodispatch
115:
116: mov.l #Csym(knl_ctxtsk), r1 /* Is dispatch required? */
117: mov.l [r1], r1
118: mov.l #Csym(knl_schedtsk), r2
119: mov.l [r2], r2
120: cmp r1, r2
121: beq l_nodispatch
122:
123: popm r1-r2 /* R1, R2 restore */
124: bra Csym(ret_int_dispatch) /* To dispatch processing */
125:
126: l_nodispatch: /* Dispatch not required */
127: popm r1-r2 /* R1, R2 restore */
128: rte
129:
130: .end
131:
132: #endif /* CPU_CORE_RXV2 */