gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.04
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/05/17.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_CORE_RXV2
   16: 
   17: /*
   18:  *      vector_tbl.h (RXv2)
   19:  *      Exception Vector Table
   20:  */
   21: 
   22: #include "kernel.h"
   23: #include "../../../sysdepend.h"
   24: 
   25: /* ------------------------------------------------------------------------ */
   26: /*
   27:  * Reset Vector
   28:  * 
   29:  */
   30: 
   31: void (* const reset_vect[])()  __attribute__((section (".fvectors"))) = {
   32:         Reset_Handler,                         /* Power On Reset */
   33: };
   34: 
   35: /* ------------------------------------------------------------------------ */
   36: /*
   37:  * Exception Vector Table
   38:  * 
   39:  */
   40: 
   41: void (* const exvect_tbl[])()  __attribute__((section(".exvectors"))) = {
   42:         (void(*)())(0xffffffff),               /* MDES  Endian Select Register */
   43:         0,
   44:         (void(*)())(0xffffffff),               /* OFS1 Option function */
   45:         (void(*)())(0xffffffff),               /* OFS0 Option function */
   46:         0,
   47:         0,
   48:         0,
   49:         0,
   50:         (void(*)())(0xffffffff),               /* ID Code */
   51:         (void(*)())(0xffffffff),               /* ID Code */
   52:         (void(*)())(0xffffffff),               /* ID Code */
   53:         (void(*)())(0xffffffff),               /* ID Code */
   54:         0,
   55:         0,
   56:         0,
   57:         0,
   58:         0,
   59:         0,
   60:         0,
   61:         0,
   62:         SuperVisorInst_Handler,                        /* Supervisor Instruction Exception */
   63:         AccessInst_Handler,                    /* Access Instruction Exception */
   64:         0,
   65:         UndefinedInst_Handler,                 /*  Undefined Instruction Exception */
   66:         0,
   67:         FloatingPoint_Handler,                 /* Floating Point Exception */
   68:         0,
   69:         0,
   70:         0,
   71:         0,
   72:         NMI_Handler,                           /* Non Maskable Interrupt */
   73: };
   74: 
   75: #endif /* CPU_CORE_RXV2 */