gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.04
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/05/17.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_RX231
   16: 
   17: /*
   18:  *      hllint_tbl.c (RX231)
   19:  *      HLL Interrupt Handler Table (ROM)
   20:  */
   21: 
   22: #include "kernel.h"
   23: #include "../../sysdepend.h"
   24: 
   25: /* ------------------------------------------------------------------------ */
   26: /*
   27:  * HLL Interrupt Handler Table (ROM)
   28:  * 
   29:  */
   30: EXPORT void (* const knl_hll_inthdr_rom[])()  __attribute__((section(".hvectors"))) = {
   31:         Default_Handler,                       /* Unconditional trap */
   32:         Default_Handler,                       /* Dispatch */
   33:         Default_Handler,                       /* System call (reserved) */
   34:         Default_Handler,                       /* System call : tk_ret_int */
   35:         Default_Handler,                       /* Debugger support (reserved) */
   36:         Default_Handler,                       /* INT 5 */
   37:         Default_Handler,                       /* INT 6 */
   38:         Default_Handler,                       /* INT 7 */
   39:         Default_Handler,                       /* INT 8 */
   40:         Default_Handler,                       /* INT 9 */
   41:         Default_Handler,                       /* INT 10 */
   42:         Default_Handler,                       /* INT 11 */
   43:         Default_Handler,                       /* INT 12 */
   44:         Default_Handler,                       /* INT 13 */
   45:         Default_Handler,                       /* INT 14 */
   46:         Default_Handler,                       /* INT 15 */
   47:         Default_Handler,                       /* BSC_BUSERR */
   48:         Default_Handler,                       /* INT 17 */
   49:         Default_Handler,                       /* INT 18 */
   50:         Default_Handler,                       /* INT 19 */
   51:         Default_Handler,                       /* INT 20 */
   52:         Default_Handler,                       /* INT 21 */
   53:         Default_Handler,                       /* INT 22 */
   54:         Default_Handler,                       /* FCU_FRDYI */
   55:         Default_Handler,                       /* INT 24 */
   56:         Default_Handler,                       /* INT 25 */
   57:         Default_Handler,                       /* INT 26 */
   58:         Default_Handler,                       /* ICU_SWINT */
   59:         knl_timer_handler,                     /* CMT0_CMI0 **** System timer *****/
   60:         Default_Handler,                       /* CMT0_CMI1 */
   61:         Default_Handler,                       /* CMT0_CMI2 */
   62:         Default_Handler,                       /* CMT0_CMI3 */
   63:         Default_Handler,                       /* CAC_FERRF */
   64:         Default_Handler,                       /* CAC_MENDF */
   65:         Default_Handler,                       /* CAC_OVFF */
   66:         Default_Handler,                       /* INT 35 */
   67:         Default_Handler,                       /* USB0_D0FIFO0 */
   68:         Default_Handler,                       /* USB0_D1FIFO0 */
   69:         Default_Handler,                       /* USB0_USBI0*/
   70:         Default_Handler,                       /* INT 39 */
   71:         Default_Handler,                       /* SDHI_SBFAI */
   72:         Default_Handler,                       /* SDHI_CDETI */
   73:         Default_Handler,                       /* SDHI_CACI */
   74:         Default_Handler,                       /* SDHI_SDACI */
   75:         Default_Handler,                       /* RSPI0_SPEI0 */
   76:         Default_Handler,                       /* RSPI0_SPRI0 */
   77:         Default_Handler,                       /* RSPI0_SPTI0 */
   78:         Default_Handler,                       /* RSPI0_SPII0 */
   79:         Default_Handler,                       /* INT 48 */
   80:         Default_Handler,                       /* INT 49 */
   81:         Default_Handler,                       /* INT 50 */
   82:         Default_Handler,                       /* INT 51 */
   83:         Default_Handler,                       /* RSCAN_COMFRXINT */
   84:         Default_Handler,                       /* RSCAN_RXFINT */
   85:         Default_Handler,                       /* RSCAN_TXINT */
   86:         Default_Handler,                       /* RSCAN_CHERRINT */
   87:         Default_Handler,                       /* RSCAN_GLERRINT */
   88:         Default_Handler,                       /* DOC_DOPCF */
   89:         Default_Handler,                       /* CMPB_CMPB0 */
   90:         Default_Handler,                       /* CMPB_CMPB1 */
   91:         Default_Handler,                       /* CTSU_CTSUWR */
   92:         Default_Handler,                       /* CTSU_CTSURD */
   93:         Default_Handler,                       /* CTSU_CTSUFN */
   94:         Default_Handler,                       /* RTC_CUP */
   95:         Default_Handler,                       /* ICU_IRQ0 */
   96:         Default_Handler,                       /* ICU_IRQ1 */
   97:         Default_Handler,                       /* ICU_IRQ2 */
   98:         Default_Handler,                       /* ICU_IRQ3 */
   99:         Default_Handler,                       /* ICU_IRQ4 */
  100:         Default_Handler,                       /* ICU_IRQ5 */
  101:         Default_Handler,                       /* ICU_IRQ6 */
  102:         Default_Handler,                       /* ICU_IRQ7 */
  103:         Default_Handler,                       /* INT 72 */
  104:         Default_Handler,                       /* INT 73 */
  105:         Default_Handler,                       /* INT 74 */
  106:         Default_Handler,                       /* INT 75 */
  107:         Default_Handler,                       /* INT 76 */
  108:         Default_Handler,                       /* INT 77 */
  109:         Default_Handler,                       /* INT 78 */
  110:         Default_Handler,                       /* INT 79 */
  111:         Default_Handler,                       /* ELC_ELSR8I */
  112:         Default_Handler,                       /* INT 81 */
  113:         Default_Handler,                       /* INT 82 */
  114:         Default_Handler,                       /* INT 83 */
  115:         Default_Handler,                       /* INT 84 */
  116:         Default_Handler,                       /* INT 85 */
  117:         Default_Handler,                       /* INT 86 */
  118:         Default_Handler,                       /* INT 87 */
  119:         Default_Handler,                       /* LVD_LVD1 */
  120:         Default_Handler,                       /* LVD_LVD2 */
  121:         Default_Handler,                       /* USB0_USBR0 */
  122:         Default_Handler,                       /* VBATT_VBTLVDI */
  123:         Default_Handler,                       /* RTC_ALM */
  124:         Default_Handler,                       /* RTC_PRD */
  125:         Default_Handler,                       /* INT 94 */
  126:         Default_Handler,                       /* INT 95 */
  127:         Default_Handler,                       /* INT 96 */
  128:         Default_Handler,                       /* INT 97 */
  129:         Default_Handler,                       /* INT 98 */
  130:         Default_Handler,                       /* INT 99 */
  131:         Default_Handler,                       /* INT 100 */
  132:         Default_Handler,                       /* INT 101 */
  133:         Default_Handler,                       /* S12AD_S12ADI0 */
  134:         Default_Handler,                       /* S12AD_GBADI */
  135:         Default_Handler,                       /* CMPB1_CMPB2 */
  136:         Default_Handler,                       /* CMPB1_CMPB3 */
  137:         Default_Handler,                       /* ELC_ELSR18I */
  138:         Default_Handler,                       /* ELC_ELSR19I */
  139:         Default_Handler,                       /* SSI0_SSIF0 */
  140:         Default_Handler,                       /* SSI0_SSIRXI0 */
  141:         Default_Handler,                       /* SSI0_SSITXI0 */
  142:         Default_Handler,                       /* Secure_RD */
  143:         Default_Handler,                       /* Secure_WR */
  144:         Default_Handler,                       /* Secure_Error */
  145:         Default_Handler,                       /* MTU0_TGIA0 */
  146:         Default_Handler,                       /* MTU0_TGIB0 */
  147:         Default_Handler,                       /* MTU0_TGIC0 */
  148:         Default_Handler,                       /* MTU0_TGID0 */
  149:         Default_Handler,                       /* MTU0_TCIV0 */
  150:         Default_Handler,                       /* MTU0_TGIE0 */
  151:         Default_Handler,                       /* MTU0_TGIF0 */
  152:         Default_Handler,                       /* MTU1_TGIA1 */
  153:         Default_Handler,                       /* MTU1_TGIB1 */
  154:         Default_Handler,                       /* MTU1_TCIV1 */
  155:         Default_Handler,                       /* MTU1_TCIU1 */
  156:         Default_Handler,                       /* MTU2_TGIA2 */
  157:         Default_Handler,                       /* MTU2_TGIB2 */
  158:         Default_Handler,                       /* MTU2_TCIV2 */
  159:         Default_Handler,                       /* MTU2_TCIU2 */
  160:         Default_Handler,                       /* MTU3_TGIA3 */
  161:         Default_Handler,                       /* MTU3_TGIB3 */
  162:         Default_Handler,                       /* MTU3_TGIC3 */
  163:         Default_Handler,                       /* MTU3_TGID3 */
  164:         Default_Handler,                       /* MTU3_TCIV3 */
  165:         Default_Handler,                       /* MTU4_TGIA4 */
  166:         Default_Handler,                       /* MTU4_TGIB4 */
  167:         Default_Handler,                       /* MTU4_TGIC4 */
  168:         Default_Handler,                       /* MTU4_TGID4 */
  169:         Default_Handler,                       /* MTU4_TCIV4 */
  170:         Default_Handler,                       /* MTU5_TGIU5 */
  171:         Default_Handler,                       /* MTU5_TGIV5 */
  172:         Default_Handler,                       /* MTU5_TGIW5 */
  173:         Default_Handler,                       /* TPU0_TGI0A */
  174:         Default_Handler,                       /* TPU0_TGI0B */
  175:         Default_Handler,                       /* TPU0_TGI0C */
  176:         Default_Handler,                       /* TPU0_TGI0D */
  177:         Default_Handler,                       /* TPU0_TCI0V */
  178:         Default_Handler,                       /* TPU1_TGI1A */
  179:         Default_Handler,                       /* TPU1_TGI1B */
  180:         Default_Handler,                       /* TPU1_TCI1V */
  181:         Default_Handler,                       /* TPU1_TCI1U */
  182:         Default_Handler,                       /* TPU2_TGI2A */
  183:         Default_Handler,                       /* TPU2_TGI2B */
  184:         Default_Handler,                       /* TPU2_TCI2V */
  185:         Default_Handler,                       /* TPU2_TCI2U */
  186:         Default_Handler,                       /* TPU3_TGI3A */
  187:         Default_Handler,                       /* TPU3_TGI3B */
  188:         Default_Handler,                       /* TPU3_TGI3C */
  189:         Default_Handler,                       /* TPU3_TGI3D */
  190:         Default_Handler,                       /* TPU3_TCI3V */
  191:         Default_Handler,                       /* TPU4_TGI4A */
  192:         Default_Handler,                       /* TPU4_TGI4B */
  193:         Default_Handler,                       /* TPU4_TCI4V */
  194:         Default_Handler,                       /* TPU4_TCI4U */
  195:         Default_Handler,                       /* TPU5_TGI5A */
  196:         Default_Handler,                       /* TPU5_TGI5B */
  197:         Default_Handler,                       /* TPU5_TCI5V */
  198:         Default_Handler,                       /* TPU5_TCI5U */
  199:         Default_Handler,                       /* INT 168 */
  200:         Default_Handler,                       /* INT 169 */
  201:         Default_Handler,                       /* POE_OEI1 */
  202:         Default_Handler,                       /* POE_OEI2 */
  203:         Default_Handler,                       /* INT 172 */
  204:         Default_Handler,                       /* INT 173 */
  205:         Default_Handler,                       /* TMR0_CMIA0 */
  206:         Default_Handler,                       /* TMR0_CMIB0 */
  207:         Default_Handler,                       /* TMR0_OVI0 */
  208:         Default_Handler,                       /* TMR1_CMIA1 */
  209:         Default_Handler,                       /* TMR1_CMIB1 */
  210:         Default_Handler,                       /* TMR1_OVI1 */
  211:         Default_Handler,                       /* TMR2_CMIA2 */
  212:         Default_Handler,                       /* TMR2_CMIB2 */
  213:         Default_Handler,                       /* TMR2_OVI2 */
  214:         Default_Handler,                       /* TMR3_CMIA3 */
  215:         Default_Handler,                       /* TMR3_CMIB3 */
  216:         Default_Handler,                       /* TMR3_OVI3 */
  217:         Default_Handler,                       /* INT 186 */
  218:         Default_Handler,                       /* INT 187 */
  219:         Default_Handler,                       /* INT 188 */
  220:         Default_Handler,                       /* INT 189 */
  221:         Default_Handler,                       /* INT 190 */
  222:         Default_Handler,                       /* INT 191 */
  223:         Default_Handler,                       /* INT 192 */
  224:         Default_Handler,                       /* INT 193 */
  225:         Default_Handler,                       /* INT 194 */
  226:         Default_Handler,                       /* INT 195 */
  227:         Default_Handler,                       /* INT 196 */
  228:         Default_Handler,                       /* INT 197 */
  229:         Default_Handler,                       /* DMAC_DMAC0I*/
  230:         Default_Handler,                       /* DMAC_DMAC1I*/
  231:         Default_Handler,                       /* DMAC_DMAC2I*/
  232:         Default_Handler,                       /* DMAC_DMAC3I*/
  233:         Default_Handler,                       /* INT 202 */
  234:         Default_Handler,                       /* INT 203 */
  235:         Default_Handler,                       /* INT 204 */
  236:         Default_Handler,                       /* INT 205 */
  237:         Default_Handler,                       /* INT 206 */
  238:         Default_Handler,                       /* INT 207 */
  239:         Default_Handler,                       /* INT 208 */
  240:         Default_Handler,                       /* INT 209 */
  241:         Default_Handler,                       /* INT 210 */
  242:         Default_Handler,                       /* INT 211 */
  243:         Default_Handler,                       /* INT 212 */
  244:         Default_Handler,                       /* INT 213 */
  245:         Default_Handler,                       /* SCI0_ERI0 */
  246:         Default_Handler,                       /* SCI0_RXI0 */
  247:         Default_Handler,                       /* SCI0_TXI0 */
  248:         Default_Handler,                       /* SCI0_TEI0 */
  249:         Default_Handler,                       /* SCI1_ERI1 */
  250:         Default_Handler,                       /* SCI1_RXI1 */
  251:         Default_Handler,                       /* SCI1_TXI1 */
  252:         Default_Handler,                       /* SCI1_TEI1 */
  253:         Default_Handler,                       /* SCI5_ERI5 */
  254:         Default_Handler,                       /* SCI5_RXI5 */
  255:         Default_Handler,                       /* SCI5_TXI5 */
  256:         Default_Handler,                       /* SCI5_TEI5 */
  257:         Default_Handler,                       /* SCI6_ERI6 */
  258:         Default_Handler,                       /* SCI6_RXI6 */
  259:         Default_Handler,                       /* SCI6_TXI6 */
  260:         Default_Handler,                       /* SCI6_TEI6 */
  261:         Default_Handler,                       /* SCI8_ERI8 */
  262:         Default_Handler,                       /* SCI8_RXI8 */
  263:         Default_Handler,                       /* SCI8_TXI8 */
  264:         Default_Handler,                       /* SCI8_TEI8 */
  265:         Default_Handler,                       /* SCI9_ERI9 */
  266:         Default_Handler,                       /* SCI9_RXI9 */
  267:         Default_Handler,                       /* SCI9_TXI9 */
  268:         Default_Handler,                       /* SCI9_TEI9 */
  269:         Default_Handler,                       /* SCI12_ERI12 */
  270:         Default_Handler,                       /* SCI12_RXI12 */
  271:         Default_Handler,                       /* SCI12_TXI12 */
  272:         Default_Handler,                       /* SCI12_TEI12 */
  273:         Default_Handler,                       /* SCI12_SCIX0 */
  274:         Default_Handler,                       /* SCI12_SCIX1 */
  275:         Default_Handler,                       /* SCI12_SCIX2 */
  276:         Default_Handler,                       /* SCI12_SCIX3 */
  277:         Default_Handler,                       /* RIIC0_EEI0 */
  278:         Default_Handler,                       /* RIIC0_RXI0 */
  279:         Default_Handler,                       /* RIIC0_TXI0 */
  280:         Default_Handler,                       /* RIIC0_TEI0 */
  281:         Default_Handler,                       /* INT 250 */
  282:         Default_Handler,                       /* INT 251 */
  283:         Default_Handler,                       /* INT 252 */
  284:         Default_Handler,                       /* INT 253 */
  285:         Default_Handler,                       /* INT 254 */
  286:         Default_Handler,                       /* INT 255 */
  287: };
  288: 
  289: #endif /* CPU_CORE_RX231 */