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    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.04
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/05/17.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_RX231
   16: 
   17: /*
   18:  *      intvect_tbl.c (RX231)
   19:  *      Interrupt Vector Table (ROM)
   20:  */
   21: 
   22: #include "kernel.h"
   23: #include "../../sysdepend.h"
   24: 
   25: #include "hllint_ent.h"
   26: 
   27: /* ------------------------------------------------------------------------ */
   28: /*
   29:  * Interrupt Vector Table (ROM)
   30:  * 
   31:  */
   32: EXPORT void (* const knl_int_vect_rom[])()  __attribute__((section(".rvectors"))) = {
   33:         hll_inthdr_entry_0,                    /* Unconditional trap */
   34:         hll_inthdr_entry_1,                    /* Dispatch */
   35:         hll_inthdr_entry_2,                    /* System call (reserved) */
   36:         hll_inthdr_entry_3,                    /* System call : tk_ret_int */
   37:         hll_inthdr_entry_4,                    /* Debugger support (reserved) */
   38:         hll_inthdr_entry_5,                    /* INT 5 */
   39:         hll_inthdr_entry_6,                    /* INT 6 */
   40:         hll_inthdr_entry_7,                    /* INT 7 */
   41:         hll_inthdr_entry_8,                    /* INT 8 */
   42:         hll_inthdr_entry_9,                    /* INT 9 */
   43:         hll_inthdr_entry_10,                   /* INT 10 */
   44:         hll_inthdr_entry_11,                   /* INT 11 */
   45:         hll_inthdr_entry_12,                   /* INT 12 */
   46:         hll_inthdr_entry_13,                   /* INT 13 */
   47:         hll_inthdr_entry_14,                   /* INT 14 */
   48:         hll_inthdr_entry_15,                   /* INT 15 */
   49:         hll_inthdr_entry_16,                   /* BSC_BUSERR */
   50:         hll_inthdr_entry_17,                   /* INT 17 */
   51:         hll_inthdr_entry_18,                   /* INT 18 */
   52:         hll_inthdr_entry_19,                   /* INT 19 */
   53:         hll_inthdr_entry_20,                   /* INT 20 */
   54:         hll_inthdr_entry_21,                   /* INT 21 */
   55:         hll_inthdr_entry_22,                   /* INT 22 */
   56:         hll_inthdr_entry_23,                   /* FCU_FRDYI */
   57:         hll_inthdr_entry_24,                   /* INT 24 */
   58:         hll_inthdr_entry_25,                   /* INT 25 */
   59:         hll_inthdr_entry_26,                   /* INT 26 */
   60:         hll_inthdr_entry_27,                   /* ICU_SWINT */
   61:         hll_inthdr_entry_28,                   /* CMT0_CMI0 */
   62:         hll_inthdr_entry_29,                   /* CMT0_CMI1 */
   63:         hll_inthdr_entry_30,                   /* CMT0_CMI2 */
   64:         hll_inthdr_entry_31,                   /* CMT0_CMI3 */
   65:         hll_inthdr_entry_32,                   /* CAC_FERRF */
   66:         hll_inthdr_entry_33,                   /* CAC_MENDF */
   67:         hll_inthdr_entry_34,                   /* CAC_OVFF */
   68:         hll_inthdr_entry_35,                   /* INT 35 */
   69:         hll_inthdr_entry_36,                   /* USB0_D0FIFO0 */
   70:         hll_inthdr_entry_37,                   /* USB0_D1FIFO0 */
   71:         hll_inthdr_entry_38,                   /* USB0_USBI0*/
   72:         hll_inthdr_entry_39,                   /* INT 39 */
   73:         hll_inthdr_entry_40,                   /* SDHI_SBFAI */
   74:         hll_inthdr_entry_41,                   /* SDHI_CDETI */
   75:         hll_inthdr_entry_42,                   /* SDHI_CACI */
   76:         hll_inthdr_entry_43,                   /* SDHI_SDACI */
   77:         hll_inthdr_entry_44,                   /* RSPI0_SPEI0 */
   78:         hll_inthdr_entry_45,                   /* RSPI0_SPRI0 */
   79:         hll_inthdr_entry_46,                   /* RSPI0_SPTI0 */
   80:         hll_inthdr_entry_47,                   /* RSPI0_SPII0 */
   81:         hll_inthdr_entry_48,                   /* INT 48 */
   82:         hll_inthdr_entry_49,                   /* INT 49 */
   83:         hll_inthdr_entry_50,                   /* INT 50 */
   84:         hll_inthdr_entry_51,                   /* INT 51 */
   85:         hll_inthdr_entry_52,                   /* RSCAN_COMFRXINT */
   86:         hll_inthdr_entry_53,                   /* RSCAN_RXFINT */
   87:         hll_inthdr_entry_54,                   /* RSCAN_TXINT */
   88:         hll_inthdr_entry_55,                   /* RSCAN_CHERRINT */
   89:         hll_inthdr_entry_56,                   /* RSCAN_GLERRINT */
   90:         hll_inthdr_entry_57,                   /* DOC_DOPCF */
   91:         hll_inthdr_entry_58,                   /* CMPB_CMPB0 */
   92:         hll_inthdr_entry_59,                   /* CMPB_CMPB1 */
   93:         hll_inthdr_entry_60,                   /* CTSU_CTSUWR */
   94:         hll_inthdr_entry_61,                   /* CTSU_CTSURD */
   95:         hll_inthdr_entry_62,                   /* CTSU_CTSUFN */
   96:         hll_inthdr_entry_63,                   /* RTC_CUP */
   97:         hll_inthdr_entry_64,                   /* ICU_IRQ0 */
   98:         hll_inthdr_entry_65,                   /* ICU_IRQ1 */
   99:         hll_inthdr_entry_66,                   /* ICU_IRQ2 */
  100:         hll_inthdr_entry_67,                   /* ICU_IRQ3 */
  101:         hll_inthdr_entry_68,                   /* ICU_IRQ4 */
  102:         hll_inthdr_entry_69,                   /* ICU_IRQ5 */
  103:         hll_inthdr_entry_70,                   /* ICU_IRQ6 */
  104:         hll_inthdr_entry_71,                   /* ICU_IRQ7 */
  105:         hll_inthdr_entry_72,                   /* INT 72 */
  106:         hll_inthdr_entry_73,                   /* INT 73 */
  107:         hll_inthdr_entry_74,                   /* INT 74 */
  108:         hll_inthdr_entry_75,                   /* INT 75 */
  109:         hll_inthdr_entry_76,                   /* INT 76 */
  110:         hll_inthdr_entry_77,                   /* INT 77 */
  111:         hll_inthdr_entry_78,                   /* INT 78 */
  112:         hll_inthdr_entry_79,                   /* INT 79 */
  113:         hll_inthdr_entry_80,                   /* ELC_ELSR8I */
  114:         hll_inthdr_entry_81,                   /* INT 81 */
  115:         hll_inthdr_entry_82,                   /* INT 82 */
  116:         hll_inthdr_entry_83,                   /* INT 83 */
  117:         hll_inthdr_entry_84,                   /* INT 84 */
  118:         hll_inthdr_entry_85,                   /* INT 85 */
  119:         hll_inthdr_entry_86,                   /* INT 86 */
  120:         hll_inthdr_entry_87,                   /* INT 87 */
  121:         hll_inthdr_entry_88,                   /* LVD_LVD1 */
  122:         hll_inthdr_entry_89,                   /* LVD_LVD2 */
  123:         hll_inthdr_entry_90,                   /* USB0_USBR0 */
  124:         hll_inthdr_entry_91,                   /* VBATT_VBTLVDI */
  125:         hll_inthdr_entry_92,                   /* RTC_ALM */
  126:         hll_inthdr_entry_93,                   /* RTC_PRD */
  127:         hll_inthdr_entry_94,                   /* INT 94 */
  128:         hll_inthdr_entry_95,                   /* INT 95 */
  129:         hll_inthdr_entry_96,                   /* INT 96 */
  130:         hll_inthdr_entry_97,                   /* INT 97 */
  131:         hll_inthdr_entry_98,                   /* INT 98 */
  132:         hll_inthdr_entry_99,                   /* INT 99 */
  133:         hll_inthdr_entry_100,                  /* INT 100 */
  134:         hll_inthdr_entry_101,                  /* INT 101 */
  135:         hll_inthdr_entry_102,                  /* S12AD_S12ADI0 */
  136:         hll_inthdr_entry_103,                  /* S12AD_GBADI */
  137:         hll_inthdr_entry_104,                  /* CMPB1_CMPB2 */
  138:         hll_inthdr_entry_105,                  /* CMPB1_CMPB3 */
  139:         hll_inthdr_entry_106,                  /* ELC_ELSR18I */
  140:         hll_inthdr_entry_107,                  /* ELC_ELSR19I */
  141:         hll_inthdr_entry_108,                  /* SSI0_SSIF0 */
  142:         hll_inthdr_entry_109,                  /* SSI0_SSIRXI0 */
  143:         hll_inthdr_entry_110,                  /* SSI0_SSITXI0 */
  144:         hll_inthdr_entry_111,                  /* Secure_RD */
  145:         hll_inthdr_entry_112,                  /* Secure_WR */
  146:         hll_inthdr_entry_113,                  /* Secure_Error */
  147:         hll_inthdr_entry_114,                  /* MTU0_TGIA0 */
  148:         hll_inthdr_entry_115,                  /* MTU0_TGIB0 */
  149:         hll_inthdr_entry_116,                  /* MTU0_TGIC0 */
  150:         hll_inthdr_entry_117,                  /* MTU0_TGID0 */
  151:         hll_inthdr_entry_118,                  /* MTU0_TCIV0 */
  152:         hll_inthdr_entry_119,                  /* MTU0_TGIE0 */
  153:         hll_inthdr_entry_120,                  /* MTU0_TGIF0 */
  154:         hll_inthdr_entry_121,                  /* MTU1_TGIA1 */
  155:         hll_inthdr_entry_122,                  /* MTU1_TGIB1 */
  156:         hll_inthdr_entry_123,                  /* MTU1_TCIV1 */
  157:         hll_inthdr_entry_124,                  /* MTU1_TCIU1 */
  158:         hll_inthdr_entry_125,                  /* MTU2_TGIA2 */
  159:         hll_inthdr_entry_126,                  /* MTU2_TGIB2 */
  160:         hll_inthdr_entry_127,                  /* MTU2_TCIV2 */
  161:         hll_inthdr_entry_128,                  /* MTU2_TCIU2 */
  162:         hll_inthdr_entry_129,                  /* MTU3_TGIA3 */
  163:         hll_inthdr_entry_130,                  /* MTU3_TGIB3 */
  164:         hll_inthdr_entry_131,                  /* MTU3_TGIC3 */
  165:         hll_inthdr_entry_132,                  /* MTU3_TGID3 */
  166:         hll_inthdr_entry_133,                  /* MTU3_TCIV3 */
  167:         hll_inthdr_entry_134,                  /* MTU4_TGIA4 */
  168:         hll_inthdr_entry_135,                  /* MTU4_TGIB4 */
  169:         hll_inthdr_entry_136,                  /* MTU4_TGIC4 */
  170:         hll_inthdr_entry_137,                  /* MTU4_TGID4 */
  171:         hll_inthdr_entry_138,                  /* MTU4_TCIV4 */
  172:         hll_inthdr_entry_139,                  /* MTU5_TGIU5 */
  173:         hll_inthdr_entry_140,                  /* MTU5_TGIV5 */
  174:         hll_inthdr_entry_141,                  /* MTU5_TGIW5 */
  175:         hll_inthdr_entry_142,                  /* TPU0_TGI0A */
  176:         hll_inthdr_entry_143,                  /* TPU0_TGI0B */
  177:         hll_inthdr_entry_144,                  /* TPU0_TGI0C */
  178:         hll_inthdr_entry_145,                  /* TPU0_TGI0D */
  179:         hll_inthdr_entry_146,                  /* TPU0_TCI0V */
  180:         hll_inthdr_entry_147,                  /* TPU1_TGI1A */
  181:         hll_inthdr_entry_148,                  /* TPU1_TGI1B */
  182:         hll_inthdr_entry_149,                  /* TPU1_TCI1V */
  183:         hll_inthdr_entry_150,                  /* TPU1_TCI1U */
  184:         hll_inthdr_entry_151,                  /* TPU2_TGI2A */
  185:         hll_inthdr_entry_152,                  /* TPU2_TGI2B */
  186:         hll_inthdr_entry_153,                  /* TPU2_TCI2V */
  187:         hll_inthdr_entry_154,                  /* TPU2_TCI2U */
  188:         hll_inthdr_entry_155,                  /* TPU3_TGI3A */
  189:         hll_inthdr_entry_156,                  /* TPU3_TGI3B */
  190:         hll_inthdr_entry_157,                  /* TPU3_TGI3C */
  191:         hll_inthdr_entry_158,                  /* TPU3_TGI3D */
  192:         hll_inthdr_entry_159,                  /* TPU3_TCI3V */
  193:         hll_inthdr_entry_160,                  /* TPU4_TGI4A */
  194:         hll_inthdr_entry_161,                  /* TPU4_TGI4B */
  195:         hll_inthdr_entry_162,                  /* TPU4_TCI4V */
  196:         hll_inthdr_entry_163,                  /* TPU4_TCI4U */
  197:         hll_inthdr_entry_164,                  /* TPU5_TGI5A */
  198:         hll_inthdr_entry_165,                  /* TPU5_TGI5B */
  199:         hll_inthdr_entry_166,                  /* TPU5_TCI5V */
  200:         hll_inthdr_entry_167,                  /* TPU5_TCI5U */
  201:         hll_inthdr_entry_168,                  /* INT 168 */
  202:         hll_inthdr_entry_169,                  /* INT 169 */
  203:         hll_inthdr_entry_170,                  /* POE_OEI1 */
  204:         hll_inthdr_entry_171,                  /* POE_OEI2 */
  205:         hll_inthdr_entry_172,                  /* INT 172 */
  206:         hll_inthdr_entry_173,                  /* INT 173 */
  207:         hll_inthdr_entry_174,                  /* TMR0_CMIA0 */
  208:         hll_inthdr_entry_175,                  /* TMR0_CMIB0 */
  209:         hll_inthdr_entry_176,                  /* TMR0_OVI0 */
  210:         hll_inthdr_entry_177,                  /* TMR1_CMIA1 */
  211:         hll_inthdr_entry_178,                  /* TMR1_CMIB1 */
  212:         hll_inthdr_entry_179,                  /* TMR1_OVI1 */
  213:         hll_inthdr_entry_180,                  /* TMR2_CMIA2 */
  214:         hll_inthdr_entry_181,                  /* TMR2_CMIB2 */
  215:         hll_inthdr_entry_182,                  /* TMR2_OVI2 */
  216:         hll_inthdr_entry_183,                  /* TMR3_CMIA3 */
  217:         hll_inthdr_entry_184,                  /* TMR3_CMIB3 */
  218:         hll_inthdr_entry_185,                  /* TMR3_OVI3 */
  219:         hll_inthdr_entry_186,                  /* INT 186 */
  220:         hll_inthdr_entry_187,                  /* INT 187 */
  221:         hll_inthdr_entry_188,                  /* INT 188 */
  222:         hll_inthdr_entry_189,                  /* INT 189 */
  223:         hll_inthdr_entry_190,                  /* INT 190 */
  224:         hll_inthdr_entry_191,                  /* INT 191 */
  225:         hll_inthdr_entry_192,                  /* INT 192 */
  226:         hll_inthdr_entry_193,                  /* INT 193 */
  227:         hll_inthdr_entry_194,                  /* INT 194 */
  228:         hll_inthdr_entry_195,                  /* INT 195 */
  229:         hll_inthdr_entry_196,                  /* INT 196 */
  230:         hll_inthdr_entry_197,                  /* INT 197 */
  231:         hll_inthdr_entry_198,                  /* DMAC_DMAC0I*/
  232:         hll_inthdr_entry_199,                  /* DMAC_DMAC1I*/
  233:         hll_inthdr_entry_209,                  /* DMAC_DMAC2I*/
  234:         hll_inthdr_entry_201,                  /* DMAC_DMAC3I*/
  235:         hll_inthdr_entry_202,                  /* INT 202 */
  236:         hll_inthdr_entry_203,                  /* INT 203 */
  237:         hll_inthdr_entry_204,                  /* INT 204 */
  238:         hll_inthdr_entry_205,                  /* INT 205 */
  239:         hll_inthdr_entry_206,                  /* INT 206 */
  240:         hll_inthdr_entry_207,                  /* INT 207 */
  241:         hll_inthdr_entry_208,                  /* INT 208 */
  242:         hll_inthdr_entry_209,                  /* INT 209 */
  243:         hll_inthdr_entry_210,                  /* INT 210 */
  244:         hll_inthdr_entry_211,                  /* INT 211 */
  245:         hll_inthdr_entry_212,                  /* INT 212 */
  246:         hll_inthdr_entry_213,                  /* INT 213 */
  247:         hll_inthdr_entry_214,                  /* SCI0_ERI0 */
  248:         hll_inthdr_entry_215,                  /* SCI0_RXI0 */
  249:         hll_inthdr_entry_216,                  /* SCI0_TXI0 */
  250:         hll_inthdr_entry_217,                  /* SCI0_TEI0 */
  251:         hll_inthdr_entry_218,                  /* SCI1_ERI1 */
  252:         hll_inthdr_entry_219,                  /* SCI1_RXI1 */
  253:         hll_inthdr_entry_220,                  /* SCI1_TXI1 */
  254:         hll_inthdr_entry_221,                  /* SCI1_TEI1 */
  255:         hll_inthdr_entry_222,                  /* SCI5_ERI5 */
  256:         hll_inthdr_entry_223,                  /* SCI5_RXI5 */
  257:         hll_inthdr_entry_224,                  /* SCI5_TXI5 */
  258:         hll_inthdr_entry_225,                  /* SCI5_TEI5 */
  259:         hll_inthdr_entry_226,                  /* SCI6_ERI6 */
  260:         hll_inthdr_entry_227,                  /* SCI6_RXI6 */
  261:         hll_inthdr_entry_228,                  /* SCI6_TXI6 */
  262:         hll_inthdr_entry_229,                  /* SCI6_TEI6 */
  263:         hll_inthdr_entry_230,                  /* SCI8_ERI8 */
  264:         hll_inthdr_entry_231,                  /* SCI8_RXI8 */
  265:         hll_inthdr_entry_232,                  /* SCI8_TXI8 */
  266:         hll_inthdr_entry_233,                  /* SCI8_TEI8 */
  267:         hll_inthdr_entry_234,                  /* SCI9_ERI9 */
  268:         hll_inthdr_entry_235,                  /* SCI9_RXI9 */
  269:         hll_inthdr_entry_236,                  /* SCI9_TXI9 */
  270:         hll_inthdr_entry_237,                  /* SCI9_TEI9 */
  271:         hll_inthdr_entry_238,                  /* SCI12_ERI12 */
  272:         hll_inthdr_entry_239,                  /* SCI12_RXI12 */
  273:         hll_inthdr_entry_240,                  /* SCI12_TXI12 */
  274:         hll_inthdr_entry_241,                  /* SCI12_TEI12 */
  275:         hll_inthdr_entry_242,                  /* SCI12_SCIX0 */
  276:         hll_inthdr_entry_243,                  /* SCI12_SCIX1 */
  277:         hll_inthdr_entry_244,                  /* SCI12_SCIX2 */
  278:         hll_inthdr_entry_245,                  /* SCI12_SCIX3 */
  279:         hll_inthdr_entry_246,                  /* RIIC0_EEI0 */
  280:         hll_inthdr_entry_247,                  /* RIIC0_RXI0 */
  281:         hll_inthdr_entry_248,                  /* RIIC0_TXI0 */
  282:         hll_inthdr_entry_249,                  /* RIIC0_TEI0 */
  283:         hll_inthdr_entry_250,                  /* INT 250 */
  284:         hll_inthdr_entry_251,                  /* INT 251 */
  285:         hll_inthdr_entry_252,                  /* INT 252 */
  286:         hll_inthdr_entry_253,                  /* INT 253 */
  287:         hll_inthdr_entry_254,                  /* INT 254 */
  288:         hll_inthdr_entry_255,                  /* INT 255 */
  289: };
  290: 
  291: #endif /* CPU_CORE_RX231 */