1: /*
2: *----------------------------------------------------------------------
3: * micro T-Kernel 3.00.05
4: *
5: * Copyright (C) 2006-2021 by Ken Sakamura.
6: * This software is distributed under the T-License 2.2.
7: *----------------------------------------------------------------------
8: *
9: * Released by TRON Forum(http://www.tron.org) at 2021/11.
10: *
11: *----------------------------------------------------------------------
12: */
13:
14: #include <sys/machine.h>
15: #ifdef CPU_RZA2M
16:
17: /*
18: * sf_bott.S (RZ/A2M)
19: * Boot Loader for Serial Flash
20: */
21:
22: #define _in_asm_source_
23: #include <sys/sysdef.h>
24:
25: /* ------------------------------------------------------------------------*/
26: /*
27: * Vector Table for Serial Flash
28: */
29: .section SF_VECTOR_TABLE, "ax"
30: .arm
31:
32: .global Csym(sf_vector_table)
33: Csym(sf_vector_table):
34: ldr pc, =sf_reset_handler // 0x0000 : Reset exception
35: ldr pc, =sf_default_entry // 0x0004 : Undefined instructions exception
36: ldr pc, =sf_default_entry // 0x0008 : Software interrupts exceptions
37: ldr pc, =sf_default_entry // 0x000c : Prefetch abort exception
38: ldr pc, =sf_default_entry // 0x0010 : Data abort exception
39: nop // 0x0014 : Reserved
40: ldr pc, =sf_default_entry // 0x0018 : IRQ exception
41: ldr pc, =sf_default_entry // 0x001c : FIQ exception
42:
43: Literals_vector:
44: .LTORG
45:
46: sf_default_entry:
47: b .
48:
49: /* ------------------------------------------------------------------------*/
50: /*
51: * Reset handler for Serial Flash
52: */
53: .section SF_RESET_HANDLER, "ax"
54: .arm
55: .global Csym(start)
56: Csym(start):
57: sf_reset_handler:
58: /* Disable IRQ, FIQ */
59: mrs r0, cpsr
60: orr r0, r0, #PSR_DI
61: msr cpsr_c, r0
62:
63: /* disable I Cache & MMU */
64: mrc p15, 0, r0, c1, c0, 0 // Read CP15 register (SCTLR)
65: bic r0, r0, #CP15_SCTLR_I // Clear I bit to disable I Cache
66: bic r0, r0, #CP15_SCTLR_C // Clear C bit to disable D Cache
67: bic r0, r0, #CP15_SCTLR_M // Clear M bit to disable MMU
68: bic r0, r0, #CP15_SCTLR_V // Clear V bit to VBAR vector
69: mcr p15, 0, r0, c1, c0, 0 // Write value back to CP15 register (SCTLR)
70: ISB // Instruction Synchronization barrier
71:
72: /* Set VBAR vector */
73: ldr r0, =sf_vector_table
74: mcr p15, 0, r0, c12, c0, 0
75:
76: /* Set stack (use temporarys stack) */
77: cps #PSR_SVC // SVC Mode
78: ldr sp, =__tmp_stack_start
79:
80: /* copy text section */
81: ldr r0, =_text_start // r0 <- text start address
82: ldr r1, =_text_size // r1 <- text_size
83: ldr r2, =_text_load // r2 <- text load address
84:
85: add r1, r1, #3
86: and r1, r1, #0xfffffffc // Rounded up
87:
88: cmp r1, #0
89: beq copy_done // if text_size == 0
90: cmp r0, r2
91: beq copy_done // if _text_start == _text_load(text section is not imaged)
92:
93: copy_loop:
94: subs r1, r1, #16 // text_size -= 16
95: ldmhsia r2!, {r8, r9, r10, r11} // if text_size >= 0
96: stmhsia r0!, {r8, r9, r10, r11} // if text_size >= 0
97: bhi copy_loop // if text_size > 0
98: beq copy_done // if text_size == 0
99:
100: add r1, r1, #16
101:
102: copy_loop2:
103: subs r1, r1, #4 // text_size -= 4
104: ldmhsia r2!, {r8} // if text_size >= 0
105: stmhsia r0!, {r8} // if text_size >= 0
106: bhi copy_loop2 // if text_size > 0
107:
108: copy_done:
109: /* clear registers */
110: mov r0, #0
111: mov r1, #0
112: mov r2, #0
113: mov r3, #0
114: mov r5, #0
115: mov r6, #0
116: mov r7, #0
117: mov r8, #0
118: mov r9, #0
119: mov r10, #0
120: mov r11, #0
121: mov r12, #0
122: /* jump to text section on RAM */
123: ldr lr, =_text_start // r0 <- text start address
124: bx lr
125:
126: #endif /* CPU_RZA2M */