gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_RZA2M
   16: 
   17: /*
   18:  *      ttb_ini.c (RZ/A2M)
   19:  *      TTB(translation table base) initial value
   20:  */
   21: #include <tk/tkernel.h>
   22: 
   23: typedef struct {
   24:         UW     addr;               /* Address */
   25:         UW     size;               /* Area size */
   26:         UW     attr;               /* Attribute*/
   27:         UW     dmy;                /* Padding */
   28: } T_TTB_VAL;
   29: 
   30: EXPORT const T_TTB_VAL  knl_ttb_ini[] = {
   31:         {0x1f000000,               0x00100000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0x1f000000 - 0x1f0fffff
   32:         {0x1f400000,               0x00100000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0x1f400000 - 0x1f4fffff
   33:         {0x1f800000,               0x00100000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0x1f800000 - 0x1f8ffff
   34:         {0x20000000,               0x02000000,         TTB_ATR_NORMAL_CACHE,     0x00000000},  // SPI multi I/O bus area (Serial flash) 0x20000000 - 0x2fffffff  32MB on board
   35:         {0x30000000,               0x00800000,         TTB_ATR_NORMAL_CACHE,     0x00000000},  // Hyper Flash area  0x30000000 - 0x3fffffff  8MB on board
   36:         {0x40000000,               0x00800000,         TTB_ATR_NORMAL_CACHE,     0x00000000},  // Hyper RAM area    0x40000000 - 0x4fffffff  8MB on board
   37:         {IRAM_CACHED_START_ADDR,   IRAM_CACHED_SIZE,   TTB_ATR_NORMAL_CACHE,     0x00000000},  // Internal RAM (CACHED) area
   38:         {IRAM_UNCACHED_START_ADDR, IRAM_UNCACHED_SIZE, TTB_ATR_NORMAL_NOT_CACHE, 0x00000000},  // Internal RAM (UBCACHED) area
   39:         {0xe8000000,               0x00300000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0xe8000000 - 0xe82fffff
   40:         {0xea000000,               0x01000000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0xea000000 - 0xea0fffff
   41:         {0xf0000000,               0x00100000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0xf0000000 - 0xf00fffff
   42:         {0xfc000000,               0x00100000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0xfc000000 - 0xfc0fffff
   43:         {0xfcf00000,               0x00100000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0xfcf00000 - 0xfcffffff
   44:         {0xfff00000,               0x00100000,         TTB_ATR_STRGLY,           0x00000000},  // Internal I/O area 0xfff00000 - 0xffffffff
   45:         {0x00000000,               0x00000000,         0x00000000,               0x00000000},  // terminate
   46: 
   47: };
   48: 
   49: #endif /* CPU_RZA2M */