gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_STM32L4
   16: 
   17: /*
   18:  *      cpu_clock.c (STM32L4)
   19:  *      Clock Setting
   20:  */
   21: 
   22: #include <tk/tkernel.h>
   23: 
   24: #include "sysdepend.h"
   25: 
   26: /*
   27:  *  Startup System Clock
   28:  */
   29: EXPORT void startup_clock(ATR clkatr)
   30: {       
   31:         UW     clk_sw, pll_src;
   32:         UW     f_ratency;
   33: 
   34:         /* Select clock */
   35:         /* Use HSI clock */
   36:         if( clkatr & CLKATR_HSI ) {
   37:                 *(_UW*)RCC_CR |= RCC_CR_HSION;                        // HSI enable
   38:                 while((*(_UW*)RCC_CR & RCC_CR_HSIRDY) == 0 ); // Wait HSI ready
   39:                 clk_sw = RCC_CFGR_SW_HSI16;
   40: 
   41:         /* Use HSE clock */
   42:         } else if( clkatr & CLKATR_HSE ) {
   43:                 *(_UW*)RCC_CR |= RCC_CR_HSEON;                        // HSE enable
   44:                 while( (*(_UW*)RCC_CR & RCC_CR_HSERDY) == 0 );        /* Wait HSE ready */
   45:                 clk_sw = RCC_CFGR_SW_HSE;
   46: 
   47:         /* Use MSI clock */
   48:         } else {
   49:                 *(_UW*)RCC_CR |= RCC_CR_MSION;                        // MSI enable
   50:                 while((*(_UW*)RCC_CR & RCC_CR_MSIRDY) == 0 ); // Wait MSI ready
   51:                 clk_sw = RCC_CFGR_SW_MSI;
   52:         }
   53: 
   54:         /* PLL  Configuration */
   55:         if(clkatr & CLKATR_USE_PLL) {
   56:                 pll_src = clk_sw + 1;
   57:                 clk_sw = RCC_CFGR_SW_PLL;
   58: 
   59:                 /* PLL Configuration */
   60:                 *(_UW*)RCC_CR &= ~RCC_CR_PLLON;                       // Disable PLL
   61:                 while((*(_UW*)RCC_CR & RCC_CR_PLLRDY) != 0 ); // Wait PLL disable
   62: 
   63:                 out_w(RCC_PLLCFGR, (RCC_PLLCFGR_INIT & ~RCC_PLLCFGR_PLLSRC) | pll_src);       // Set PLL
   64: 
   65:                 *(_UW*)RCC_CR |= RCC_CR_PLLON;                        // Enable PLL
   66:                 *(_UW*)RCC_PLLCFGR |= RCC_PLLCFGR_PLLREN;     // Enable PLL System Clock output
   67:                 while((*(_UW*)RCC_CR & RCC_CR_PLLRDY) == 0);  // Wait PLL ready
   68: 
   69:                 /* PLLSAI1 Configuration */
   70:                 *(_UW*)RCC_CR &= ~RCC_CR_PLLSAI1ON;           // Disable PLLSAI1
   71:                 while((*(_UW*)RCC_CR & RCC_CR_PLLSAI1RDY) != 0 );     // Wait PLLSAI1 disable
   72: 
   73:                 out_w(RCC_PLLSAI1CFGR, RCC_PLLSAI1CFGR_INIT); // Set PLLSAI1
   74: 
   75:                 *(_UW*)RCC_CR |= RCC_CR_PLLSAI1ON;            // Enable PLLSAI1
   76:                 while((*(_UW*)RCC_CR & RCC_CR_PLLSAI1RDY) == 0);      // Wait PLLSAI1 ready
   77: 
   78:                 /* PLLSAI2 Configuration */
   79:                 *(_UW*)RCC_CR &= ~RCC_CR_PLLSAI2ON;           // Disable PLLSAI2
   80:                 while((*(_UW*)RCC_CR & RCC_CR_PLLSAI2RDY) != 0 );     // Wait PLLSAI2 disable
   81: 
   82:                 out_w(RCC_PLLSAI1CFGR, RCC_PLLSAI2CFGR_INIT); // Set PLLSAI2
   83: 
   84:                 *(_UW*)RCC_CR |= RCC_CR_PLLSAI2ON;            // Enable PLLSAI2
   85:                 while((*(_UW*)RCC_CR & RCC_CR_PLLSAI2RDY) == 0);      // Wait PLLSAI2 ready
   86: 
   87:         }
   88: 
   89:         /* Set Flash Memory Access latency  */
   90:         f_ratency = (clkatr & CLKATR_LATENCY_MASK)>>8;
   91:         *(_UW*)FLASH_ACR = (*(_UW*)FLASH_ACR & ~FLASH_ACR_LATENCY_MASK)| FLASH_ACR_LATENCY(f_ratency);
   92:         while( (*(_UW*)FLASH_ACR & FLASH_ACR_LATENCY_MASK) != FLASH_ACR_LATENCY(f_ratency) );
   93: 
   94:         /* Set CFGR register */
   95:         out_w(RCC_CFGR, (RCC_CFGR_INIT & ~RCC_CFGR_SW) | clk_sw);
   96:         while((*(_UW*)RCC_CFGR & RCC_CFGR_SW) != clk_sw);
   97: 
   98:         /* Disable all interrupts */
   99:         out_w(RCC_CIER, 0);
  100: }
  101: 
  102: EXPORT void shutdown_clock(void)
  103: {
  104: 
  105: }
  106: 
  107: #endif /* CPU_STM32L467 */