gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: #include <sys/machine.h>
   14: #ifdef CPU_TMPM367FDFG
   15: 
   16: /*
   17:  *      cpu_clock.c (TX03-M367)
   18:  *      Clock Setting
   19:  */
   20: 
   21: #include <tk/tkernel.h>
   22: 
   23: #include "sysdepend.h"
   24: 
   25: /*
   26:  *  Startup System Clock
   27:  *    Input clock = 12MHz  Output clock = 72MHz(PLL_MODE_6X) or 48MHz(PLL_MODE_4X)
   28:  *    **** This implementation assumes 6 multiplication.
   29:  */
   30: EXPORT void startup_clock(UB pll_mode)
   31: {
   32:         _UW    *osccr     = (_UW*)CLKCTRL_CGOSCCR;
   33: 
   34:         /* Unprotect CG . */
   35:         *(_UW*)CLKCTRL_CGPROTECT = 0xC1;
   36:         
   37: 
   38:         *osccr = (*osccr | ((1 << 19) | (1 << 18) | (1 << 8))) & 0xFFFFFFF7;
   39:         
   40:         /* Warming up = 100usec */
   41:         *osccr = (*osccr & 0x000FFFFF) | (0x64 << 20) | (1);
   42:         while( (*osccr & CLKCTRL_CGOSCCR_WUEF) != 0 ) {
   43:                 ;
   44:         }
   45:         
   46:         /* External oscillator select  */
   47:         do{
   48:                 *osccr |= (1 << 17);
   49:         } while((*osccr & (1 << 17)) == 0);
   50:         
   51:         /* Internal oscillator off */
   52:         *osccr &= ~(1 << 16);
   53:         
   54:         
   55:         /* PLLON = off */
   56:         *osccr &= 0xFFFFFFFB;
   57: 
   58:         /* Specify the number of PLL multiplier factors */
   59:         if(pll_mode == PLL_MODE_4X) {
   60:                 *(_UW*)CLKCTRL_CGPLLSEL = CLKCTRL_CGPLLSEL_4X << 1;
   61:         }
   62:         else if(pll_mode == PLL_MODE_6X) {
   63:                 *(_UW*)CLKCTRL_CGPLLSEL = CLKCTRL_CGPLLSEL_6X << 1;
   64:         }
   65:         else {         /* invarid pamameter */
   66:                 return;
   67:         }
   68:         
   69:         /* Waiting for PLL stablization (100usec) */
   70:         *osccr = (*osccr & 0x000FFFFF) | CLKCTRL_CGOSCCR_WUPT(100, HISPEED_CLOCK_MHz) | (1);
   71:         while( (*osccr & CLKCTRL_CGOSCCR_WUEF) != 0 ) {
   72:                 ;
   73:         }
   74:         
   75:         /* Enable PLL operation and Wait for PLL stablization (200usec) */
   76:         *osccr = (*osccr & 0x000FFFFF) | (CLKCTRL_CGOSCCR_PLLON |
   77:                             CLKCTRL_CGOSCCR_WUPT(200, HISPEED_CLOCK_MHz) | (1));
   78:         while( (*osccr & CLKCTRL_CGOSCCR_WUEF) != 0 ) {
   79:                 ;
   80:         }
   81:         
   82:         /* PLL operation select */
   83:         *(_UW*)CLKCTRL_CGPLLSEL |= CLKCTRL_CGPLLSEL_PLLSEL;
   84:         
   85:         /* fgear = fc/2, fperiph = fgear, T0 = fperiph, SCOUT = fsys/2 */
   86:         *(_UW*)CLKCTRL_CGSYSCR = (1 << 16) | (4);
   87:         
   88:         /* Protect CG */
   89:         *(_UW*)CLKCTRL_CGPROTECT = 0xFF;
   90:         
   91:         return;
   92:         
   93: }
   94: 
   95: 
   96: EXPORT void shutdown_clock(void)
   97: {
   98: 
   99: }
  100: 
  101: #endif /* CPU_TMPM367FDFG */